On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 311-318

  Adya, Saurabh N ^a   Markov, Igor L ^a   Villarrubia, Paul G ^b  

^a University of Michigan   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA STORAGE EQUIPMENT; LOGIC GATES; MICROPROCESSOR CHIPS; OPTIMIZATION; SIMULATED ANNEALING;

BUFFER INSERTION; WHITESPACE DISTRIBUTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0346148463     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159705     Document Type: Conference Paper

References (21)

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