User-constrained test architecture design for modular SOC testing

Proceedings - Ninth IEEE European Test Symposium, ETS 2004

Volumn , Issue , 2004, Pages 80-85

  Krundel, Ludovic ^b   Goel, Sandeep Kumar ^a   Marinissen, Erik Jan ^a   Flottes, Marie Lise ^c   Rouzeyre, Bruno ^c  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b UNIV MONTPELLIER   (France)

^c LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

OPTIMIZATION ALGORITHMS; TEST ARCHITECHTURE; USER CONSTRAINTS;

ALGORITHMS; ARCHITECTURAL DESIGN; BANDWIDTH; BENCHMARKING; CONSTRAINT THEORY; ITERATIVE METHODS; OPTIMIZATION;

TESTING;

EID: 15844430648     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETSYM.2004.1347611     Document Type: Conference Paper

References (19)

1. Yervant Zorian, Erik Jan Marinissen, and Sujit Dey. Testing Embedded-Core Based System Chips. In Proceedings IEEE International Test Conference (ITC) pages 130-143, Washington, DC, October 1998.
2. Vikram lyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. In Proceedings IEEE International Test Conference (ITC), pages 1023-1032, Baltimore, MD, October 2001.
3. Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, and Steven Oostdijk. Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip. In Proceedings Design, Automation, and Test in Europe (DATE) Designers Forum, pages 108-113, Paris, France, February 2004.
4. Krishnendu Chakrabarty. Design of System-on-a-Chip Test Access Architectures Using Integer Linear Programming. In Proceedings IEEE VLSI Test Symposium (VTS), pages 127-134, Montreal, Canada, April 2000.
5. Zahra sadat Ebadi and Andre Ivanov. Design of an Optimal Test Access Architecture Using a Genetic Algorithm. In Proceedings IEEE Asian Test Symposium (ATS), pages 205-210, Kyoto, Japan, November 2001.
6. Yu Huang et al. Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design. In Proceedings IEEE Asian Test Symposium (ATS), pages 265-270, Kyoto, Japan, November 2001.
7. Vikram lyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Integrated Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling, and Tester Data Volume Reduction for SOCs. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 685-690, New Orleans, LO, June 2002.
8. Sandeep Kumar Goel and Erik Jan Marinissen. Effective and Efficient Test Architecture Design for SOCs. In Proceedings IEEE International Test Conference (ITC), pages 529-538, Baltimore, MD, October 2002.
9. Yu Huang et al. Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. In Proceedings IEEE International Test Conference (ITC), pages 74-82, Baltimore, MD, October 2002.
10. Sandeep Koranne. On Test Scheduling for Core-Based SOCs. In Proceedings International Conference on VLSI Design, pages 505-510, Bangelore, India, January 2002.
11. Sandeep Kumar Goel and Erik Jan Marinissen. Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. In Proceedings Design, Automation, and Test in Europe (DATE), pages 738-743, Munich, Germany, March 2003.
12. Erik Larsson and Hideo Fujiwara. Test Resource Partitioning and Optimization for SOC Designs. In Proceedings IEEE VLSI Test Symposium (VTS), pages 319-324, Napa, CA, April 2003.
13. Sandeep Kumar Goel and Erik Jan Marinissen. Control-Aware Test Architecture Design for Modular SOC Testing. In Proceedings IEEE European Test Workshop (ETW), pages 57-62, Maastricht, The Netherlands, May 2003.
14. Sandeep Kumar Goel and Erik Jan Marinissen. SOC Test Architecture Design for Efficient Utilization of Test Bandwidth. ACM Transactions on Design Automation of Electronic Systems, 8(4):399-429, October 2003.
15. Erik Jan Marinissen, Sandeep Kumar Goel, and Maurice Lousberg. Wrapper Design for Embedded Core Test. In Proceedings IEEE International Test Conference (ITC), pages 911-920, Atlantic City, NJ, October 2000.
16. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Efficient Wrapper/TAM Co-Optimization for Large SOCs. In Proceedings Design, Automation, and Test in Europe (DATE), pages 491-498, Paris, France, March 2002.
17. Prab Varma and Sandeep Bhatia. A Structured Test Re-Use Methodology for Core-Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 294-302, Washington, DC, October 1998.
18. Erik Jan Marinissen et al. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores. In Proceedings IEEE International Test Conference (ITC), pages 284-293, Washington, DC, October 1998.
19. Erik Jan Marinissen, Vikram Iyengar, and Krishnendu Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. In Proceedings IEEE International Test Conference (ITC), pages 519-528, Baltimore, MD, October 2002.