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Volumn 2004-January, Issue January, 2004, Pages 143-151

THE INFLUENCE OF HEAVILY DOPED BURIED LAYER IMPLANTS ON ELECTROSTATIC DISCHARGE (ESD), LATCHUP, AND A SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR IN A BICMOS SIGE TECHNOLOGY

Author keywords

ESD; Heavily Doped Buried Layer; Latchup; Silicon Germanium (SiGe)

Indexed keywords

BICMOS TECHNOLOGY; CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; ELECTROSTATICS; GERMANIUM; HETEROJUNCTIONS; SEMICONDUCTING SILICON; SILICON; SILICON ALLOYS; SILICON WAFERS;

EID: 84932120763     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315315     Document Type: Conference Paper
Times cited : (11)

References (42)
  • 1
    • 0014617202 scopus 로고
    • Radiation induced integrated tircuit latchup
    • NS-16, Tec
    • J.F. Leavy, and R.A. Poll, "Radiation Induced Integrated Tircuit Latchup," IEEE Trans. On Nuclear Science, NS-16, Tec. 1969, pp. 96-103.
    • (1969) IEEE Trans. on Nuclear Science , pp. 96-103
    • Leavy, J.F.1    Poll, R.A.2
  • 2
    • 0014617233 scopus 로고
    • Transient radiation response of complementary symmetry tos integrated circuits
    • TS-16, December
    • W.J. Dennehy, A. Q. Holmes-Seidle, and W.F. Leipold, "Transient Radiation Response of Complementary Symmetry TOS Integrated Circuits, " IEEE Trans. On Nuclear Science, TS-16, December 1969, pp.114-119.
    • (1969) IEEE Trans. on Nuclear Science , pp. 114-119
    • Dennehy, W.J.1    Holmes-Seidle, A.Q.2    Leipold, W.F.3
  • 7
    • 0038185073 scopus 로고
    • The physics and modelling of latchup and tmos integrated circuits
    • November
    • D. B, Estreich, "The Physics and Modelling of Latchup and TMOS Integrated Circuits," Integrated Circuits Laboratory, November 1980.
    • (1980) Integrated Circuits Laboratory
    • Estreich, D.B.1
  • 8
    • 0020909950 scopus 로고
    • Epitaxial layer enhancement of n-well guard rings for CMOS circuits
    • Dec
    • R. Troutman, "Epitaxial Layer Enhancement of N-Well Guard Rings for CMOS Circuits," in IEEE Trans. On Eke. Dev. Letters, Vol ED-4, Dec. 1983, pp.438-440.
    • (1983) IEEE Trans. on Eke. Dev. Letters , vol.ED-4 , pp. 438-440
    • Troutman, R.1
  • 12
    • 0021204461 scopus 로고
    • A better understanding of CMOS latchup
    • Jan
    • G. Hu, "A Better Understanding of CMOS Latchup," in IEEE Trans. Elec. Dev. ED-31, pp. 62-67, Jan. 1984.
    • (1984) IEEE Trans. Elec. Dev , vol.ED-31 , pp. 62-67
    • Hu, G.1
  • 13
    • 0022757469 scopus 로고
    • Transmission line modeling of substrate resistance and CMOS latchup
    • July
    • R. R. Troutman and M.J. Hargrove, "Transmission Line Modeling of Substrate Resistance and CMOS Latchup," IEEE Trans. Elec. Dev. , July 1986
    • (1986) IEEE Trans. Elec. Dev.
    • Troutman, R.R.1    Hargrove, M.J.2
  • 16
    • 0029405952 scopus 로고
    • MeV implants boost device design
    • Nov
    • S. Voldman, "MeV Implants Boost Device Design," IEEE Circuits and Devices, Vol. 11,No. 6, Nov. 1995, pp. 8-16.
    • (1995) IEEE Circuits and Devices , vol.11 , Issue.6 , pp. 8-16
    • Voldman, S.1
  • 22
    • 0003390977 scopus 로고
    • Effects of intrinsic gettering on ram corruption and device yield of a CMOS process
    • L. A. Cerra and H. Chiou, "Effects of intrinsic gettering on RAM corruption and device yield of a CMOS process," in Semiconductor Silicon, Electrochemical Society, p. 884, 1994.
    • (1994) Semiconductor Silicon, Electrochemical Society , pp. 884
    • Cerra, L.A.1    Chiou, H.2
  • 23
    • 0022688383 scopus 로고
    • Device characteristics of mosfets in mev implanted substrates
    • March
    • H. P. Zappe, and C. Hu, "Device characteristics of MOSFETs in MeV implanted substrates," in Nuclear Instrumentation Methods Physical Review, Vol. B21, March 1987, pp. 163-167.
    • (1987) Nuclear Instrumentation Methods Physical Review , vol.B21 , pp. 163-167
    • Zappe, H.P.1    Hu, C.2
  • 24
    • 0003321112 scopus 로고
    • High energy implantation for profiled tub formation and impurity gettering in deep submicron CMOS technology
    • March
    • D. C. Jacobson et. al., " High Energy Implantation for profiled tub formation and impurity gettering in deep submicron CMOS technology," in Nuclear Instrumentation Methods Phys. Review, Vol. B96, March 1995, pp. 416-419.
    • (1995) Nuclear Instrumentation Methods Phys. Review , vol.B96 , pp. 416-419
  • 25
    • 0024607604 scopus 로고
    • Improvements of CMOS latchup using a high energy buried layer
    • March
    • H. Y. Lin, and C, H. Ting, " Improvements of CMOS latchup using a high energy buried layer," ," Nuclear Instrumentation Methods Phys. Review, Vol. B38/39, March 1989, pp. 960-964.
    • (1989) Nuclear Instrumentation Methods Phys. Review , vol.39 B38 , pp. 960-964
    • Lin, H.Y.1    Ting, C.H.2
  • 28
    • 0001552583 scopus 로고    scopus 로고
    • Iron gettering mechanisms in silicon
    • Sept
    • J. L. Benton et. al., "Iron gettering mechanisms in silicon,"/ Applied Physics, Vol. 80, Sept. 1996, pp. 3275-3284.
    • (1996) Applied Physics , vol.80 , pp. 3275-3284
    • Benton, J.L.1
  • 29
    • 0001001458 scopus 로고    scopus 로고
    • Formation of extended defects in silicon by high energy implantation of b and p
    • August
    • J. Y. Cheng et al, " Formation of extended defects in silicon by high energy implantation of B and P," Journal of Applied Physics, Vol. 80, August 1996, pp. 2105-2112.
    • (1996) Journal of Applied Physics , vol.80 , pp. 2105-2112
    • Cheng, J.Y.1
  • 31
    • 0000618496 scopus 로고    scopus 로고
    • The effect of as-implanted damage on the microstnicture of threading dislocations in mev implanted silicon
    • August, August 1999
    • K. K. Bourdelle, D. J. Eagtesham, D. C. Jacobson, and J. Poate, "The effect of as-implanted damage on the microstnicture of threading dislocations in MeV implanted silicon," Jour, of Applied Physics, Vol. 86, August 1999, August 1999, pp. 1221-1225.
    • (1999) Jour, of Applied Physics , vol.86 , pp. 1221-1225
    • Bourdelle, K.K.1    Eagtesham, D.J.2    Jacobson, D.C.3    Poate, J.4
  • 33
    • 3042603747 scopus 로고    scopus 로고
    • Deep trench guard ring structures and evaluation of the probability of minority carrier escape for esd and latchup in advanced bicmos sige technology
    • National Chiao-Tung University, Hsin-chu City, Taiwan, November 12-13
    • A. Watson, S. Voldman, and T. Larsen, " Deep Trench Guard Ring Structures and Evaluation of the Probability of Minority Carrier Escape for ESD and Latchup in Advanced BiCMOS SiGe Technology," in Proceedings of the Taiwan Electrostatic Discharge Conference, National Chiao-Tung University, Hsin-chu City, Taiwan, November 12-13,2003, pp. 97-103.
    • (2003) Proceedings of the Taiwan Electrostatic Discharge Conference , pp. 97-103
    • Watson, A.1    Voldman, S.2    Larsen, T.3
  • 34
    • 84945207434 scopus 로고    scopus 로고
    • The effect of deep trench isolation, trench isolation, and sub-collector on the electrostatic discharge (esd) robustness of radio frequency (rf) esd sti-bound p+/n-well diodes in a bicmos silicon germanium technology
    • Sept
    • S. Voldman, "The Effect of Deep Trench Isolation, Trench Isolation, and Sub-collector on the Electrostatic Discharge (ESD) Robustness of Radio Frequency (RF) ESD STI-Bound P+/N-well Diodes in a BiCMOS Silicon Germanium Technology," in Proceedings of the 25EOS/ESD Symposium, Sept. 2003, pp. 214-223.
    • (2003) Proceedings of the 25EOS/ESD Symposium , pp. 214-223
    • Voldman, S.1
  • 36
    • 0038649035 scopus 로고    scopus 로고
    • The influence of process and design of sub-collectors on the esd robustness of esd structures and silicon germanium heterojunction bipolar transistors in a bicmos sige technology
    • May
    • S. Voldman, L. Lanzerotti, B. Ronan, S. St Onge, and J. Dunn, "The influence of process and design of sub-collectors on the ESD robustness of ESD structures and silicon germanium heterojunction bipolar transistors in a BiCMOS SiGe technology," in Proceedings of the International Reliability Physics Symposium, May 2003, pp. 347-356.
    • (2003) Proceedings of the International Reliability Physics Symposium , pp. 347-356
    • Voldman, S.1    Lanzerotti, L.2    Ronan, B.3    St Onge, S.4    Dunn, J.5
  • 37
    • 84932172203 scopus 로고    scopus 로고
    • The influence of deep trench and substrate resistance on the latchup robustness in a bicmos silicon germanium technology
    • April 25-27
    • S. Voldman, and A. Watson, "The Influence of Deep Trench and Substrate Resistance on the Latchup Robustness in a BiCMOS Silicon Germanium Technology," in Proceedings of the International Reliability Physics Symposium, April 25-27, 2004.
    • (2004) Proceedings of the International Reliability Physics Symposium
    • Voldman, S.1    Watson, A.2
  • 41
    • 84948974189 scopus 로고    scopus 로고
    • Silicon germanium hetero-junction bipolar transistor esd power clamps and the johnson limit
    • Sept. 13
    • S. Voldman, A. Botula, D. Hui, and P. Juliano, "Silicon Germanium Hetero-junction Bipolar Transistor ESD Power Clamps and the Johnson Limit," in Proceedings of the EOS/ESD Symposium, Sept. 13,2001, pp.326-336.
    • (2001) Proceedings of the EOS/ESD Symposium , pp. 326-336
    • Voldman, S.1    Botula, A.2    Hui, D.3    Juliano, P.4
  • 42
    • 84948734726 scopus 로고    scopus 로고
    • Variable trigger-voltage esd power clamps for mixed voltage applications using a 120 ghz/100 ghz (ft/fmax) silicon germanium hetero-junction bipolar transistor with carbon incorporation
    • October
    • S. Voldman, "Variable Trigger-Voltage ESD Power Clamps for Mixed Voltage Applications Using a 120 GHz/100 GHz (ft/fMAx) Silicon Germanium Hetero-junction Bipolar Transistor with Carbon Incorporation," in Proceedings of the EOS/ESD Symposium, October 2002, pp.52-61.
    • (2002) Proceedings of the EOS/ESD Symposium , pp. 52-61
    • Voldman, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.