Latchup in CMOS

IEEE International Reliability Physics Symposium Proceedings

Volumn 2003-January, Issue , 2003, Pages 76-84

  Morris, Wesley ^a  

^a Silicon Engineering   (United States)

Author keywords

Buried guard ring; CMOS; Guard ring; High dose buried layer; Latchup

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DESIGN; FAILURE MODES; ION IMPLANTATION; MICROPROCESSOR CHIPS; SYSTEM-ON-CHIP;

BULK SUBSTRATES; CMOS TECHNOLOGY; GUARD-RINGS; HIGH DOSE BURIED LAYERS; LATCH-UPS; MULTIPLE POWER SUPPLY VOLTAGES; POWER SUPPLY VOLTAGE; SYSTEM ON CHIP DESIGN;

OUTAGES;

EID: 84955305764     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2003.1197724     Document Type: Conference Paper

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