16.7fA/cell tunnel-leakage-suppressed 16Mb SRAM for handling cosmic-ray-induced multi-errors

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Osada, Kenichi ^a   Saitoh, Yoshikazu ^b   Ibe, Eishi ^c   Ishibashi, Koichiro ^d  

^a Central Research Laboratory   (Japan)

^b Hitachi   (Japan)

^c Prod Eng Research Laboratory   (Japan)

^d NONE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COSMIC RAYS; ELECTRIC CURRENT CONTROL; ELECTRIC FIELDS; ELECTRIC POWER SUPPLIES TO APPARATUS; ERROR ANALYSIS; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOSFET DEVICES; THRESHOLD VOLTAGE;

ELECTRIC FIELD RELAXED SCHEME; ERROR CHECKING; GATE INDUCED DRAIN LEAKAGE CURRENT; GATE OXIDE TUNNEL LEAKAGE CURRENT; SOFT ERROR RATE;

STATIC RANDOM ACCESS STORAGE;

EID: 0038306346     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. F. Ziegler, et al., "IBM Experiments in Soft Fails in Computer Electronics (1978-1994)," IBM J. Res. Develop., vol. 40, no. 1, pp. 3-18, 1996.
2. K. Johansson, et al., "Neutron Induced Single-word Multiple-bit Upset in SRAM," IEEE Trans. Nucl. Sci., vol. 46, no. 6, pp. 1427-1433, Dec. 1999.
3. K. Osada, et al., "Universal-Vdd 0.65-2.0V 32kB Cache using Voltage-Adapted Timing-Generation Scheme and a Lithographical-Symmetric Cell," ISSCC Digest of Technical Papers, pp. 168-169, Feb. 2001.