Sub-40 nm SOI V-groove n-MOSFETs

IEEE Electron Device Letters

Volumn 23, Issue 2, 2002, Pages 100-102

  Appenzeller, Joerg ^b   Martel, R ^b   Avouris, Ph ^b   Knoch, J ^c   Scholvin, J ^c   Del Alamo, Jesus A ^a,c   Rice, P ^d   Solomon, Paul ^a,b  

^a IEEE

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d IBM ALMADEN RESEARCH CENTER   (United States)

Author keywords

Single gated device; SOI; Ultrashort channel; V groove MOSFET

Indexed keywords

ELECTRIC CURRENTS; EPITAXIAL GROWTH; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; ION IMPLANTATION; MOLECULAR BEAM EPITAXY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; TRANSCONDUCTANCE;

CHANNEL CONTACT RESISTANCE; DEVICE TO DEVICE ISOLATION; DOPANT FLUCTUATION; DOPING PROFILE; MOBILITY DEGRADATION; NEGATIVE GATE VOLTAGE; SINGLE GATED DEVICE; ULTRASHORT CHANNEL; V-GROOVE MOSFET;

MOSFET DEVICES;

EID: 0036477452     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.981319     Document Type: Article

References (9)

1. 30 nm physical gate length CMOS transistor with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays
2. 45-nm gate length CMOS technology and beyond using steep halo
3. Complementary silicide source/drain thin-body MOSFET's for the 20 nm gate length regime
4. Scheme for the fabrication of ultrashort channel metal-oxide semiconductor field-effect transistors
5. Sub-40 nm V-groove MOSFET's
6. Anisotropic etching of crystalline silicon in alkaline solutions
7. Technology for the fabrication of ultrashort channel metal-oxide-semiconductor field-effect transistors
8. Ultrathin 600°C wet thermal silicon dioxide
9. Quantum simulations of an ultrashort channel single-gated n-MOSFET on SOI