메뉴 건너뛰기




Volumn 12, Issue 12, 2004, Pages 1321-1329

Differential current-sensing for on-chip interconnects

Author keywords

Differential signaling; Noise analysis; Repeaters; Wire

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC RESISTANCE; ELECTRIC WIRE; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; SIGNALING; TELECOMMUNICATION REPEATERS;

EID: 12344326838     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.837987     Document Type: Article
Times cited : (31)

References (36)
  • 3
    • 0032683656 scopus 로고    scopus 로고
    • On-chip inductance issues in multiconductor systems
    • S. V. Morton, "On-chip inductance issues in multiconductor systems," in Proc. IEEE Design Automation Conf., 1999, pp. 921-926.
    • (1999) Proc. IEEE Design Automation Conf. , pp. 921-926
    • Morton, S.V.1
  • 6
    • 0029547914 scopus 로고
    • Interconnect scaling - The real limiter to high performance ULSI
    • M. Bohr, "Interconnect scaling - the real limiter to high performance ULSI," in Int. Electron Device Meeting, Tech. Dig., 1995, pp. 241-244.
    • (1995) Int. Electron Device Meeting, Tech. Dig. , pp. 241-244
    • Bohr, M.1
  • 8
    • 0032072770 scopus 로고    scopus 로고
    • Repeater design to reduce delay and power in resistive interconnect
    • May
    • V. Adler and E. Friedman, "Repeater design to reduce delay and power in resistive interconnect," IEEE Trans. Circuits Syst. II, pp. 607-616, May 1998.
    • (1998) IEEE Trans. Circuits Syst. II , pp. 607-616
    • Adler, V.1    Friedman, E.2
  • 9
    • 0029359666 scopus 로고
    • A comprehensive delay model for CMOS inverters
    • Aug.
    • S. Dutta, S. Shetti, and L. Lusky, "A comprehensive delay model for CMOS inverters," IEEE J. Solid-State Circuits, vol. 30, pp. 864-971, Aug. 1995.
    • (1995) IEEE J. Solid-state Circuits , vol.30 , pp. 864-971
    • Dutta, S.1    Shetti, S.2    Lusky, L.3
  • 10
    • 0033699061 scopus 로고    scopus 로고
    • Repeater insertion in deep sub-micron CMOS: Ramp-based analytical model and placement sensitivity analysis
    • A. Nalamalpu and W. Burleson, "Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis," in Proc. IEEE Int. Symp. Circuits Syst., 2000, pp. 766-769.
    • (2000) Proc. IEEE Int. Symp. Circuits Syst. , pp. 766-769
    • Nalamalpu, A.1    Burleson, W.2
  • 11
    • 0033891230 scopus 로고    scopus 로고
    • Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
    • Apr.
    • Y. Ismail and E. Friedman, "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," IEEE Trans. VLSI Syst., pp. 195-206, Apr. 2000.
    • (2000) IEEE Trans. VLSI Syst. , pp. 195-206
    • Ismail, Y.1    Friedman, E.2
  • 12
    • 0036054127 scopus 로고    scopus 로고
    • A physical model for the transient response of capacitively loaded distributed RLC interconnects
    • R. Venkatesan, J. A. Davis, and J. D. Meindl, "A physical model for the transient response of capacitively loaded distributed RLC interconnects," in Proc. IEEE Design Automation Conf., 2002, pp. 763-766.
    • (2002) Proc. IEEE Design Automation Conf. , pp. 763-766
    • Venkatesan, R.1    Davis, J.A.2    Meindl, J.D.3
  • 13
  • 14
    • 0032636952 scopus 로고    scopus 로고
    • Getting to the bottom of deep submicron II: A global paradigm
    • D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron II: A global paradigm," in Proc, Int. Symp. Physical Design, 1999, pp. 193-200.
    • (1999) Proc, Int. Symp. Physical Design , pp. 193-200
    • Sylvester, D.1    Keutzer, K.2
  • 15
    • 0003252889 scopus 로고    scopus 로고
    • Challenges and opportunities for design innovations in nanometer technologies
    • J. Cong, Challenges and opportunities for design innovations in nanometer technologies, in SRC Design Sciences Concept Paper, 1997.
    • (1997) SRC Design Sciences Concept Paper
    • Cong, J.1
  • 16
    • 0033704034 scopus 로고    scopus 로고
    • Low-swing on-chip signaling techniques: Effectiveness and robustness
    • June
    • H. Zhang, V. George, and J. Rabaey, "Low-swing on-chip signaling techniques: effectiveness and robustness," IEEE Trans. VLSI Syst., vol. 8, pp. 264-272, June 2000.
    • (2000) IEEE Trans. VLSI Syst. , vol.8 , pp. 264-272
    • Zhang, H.1    George, V.2    Rabaey, J.3
  • 18
    • 0011636607 scopus 로고    scopus 로고
    • Techniques for driving interconnect
    • A. Chandrakasan, W. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE Press, ch. 17
    • S. Morton, "Techniques for driving interconnect," in Design of High Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE Press, 2001, ch. 17, pp. 352-376.
    • (2001) Design of High Performance Microprocessor Circuits , pp. 352-376
    • Morton, S.1
  • 20
    • 0027259927 scopus 로고
    • Parallel regeneration of interconnects in VLSI & ULSI circuits
    • M. Nekili and Y. Savaria, "Parallel regeneration of interconnects in VLSI & ULSI circuits," in Proc. IEEE Int. Symp. Circuits Systems, 1993, pp. 2023-2026.
    • (1993) Proc. IEEE Int. Symp. Circuits Systems , pp. 2023-2026
    • Nekili, M.1    Savaria, Y.2
  • 21
    • 0036183153 scopus 로고    scopus 로고
    • Boosters for driving long on-chip interconnects: Design issues, interconnect synthesis and comparison with repeaters
    • Jan.
    • A. Nalamalpu, S. Srinivasan, and W. Burleson, "Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters," IEEE Trans. Computer-Aided Design, vol. 21, pp. 50-62, Jan. 2002.
    • (2002) IEEE Trans. Computer-aided Design , vol.21 , pp. 50-62
    • Nalamalpu, A.1    Srinivasan, S.2    Burleson, W.3
  • 22
    • 0029409835 scopus 로고
    • Regenerative feedback repeaters for programmable interconnects
    • Nov.
    • I. Dobbelaere, M. Horowitz, and A. ElGamal, "Regenerative feedback repeaters for programmable interconnects," IEEE J. Solid-State Circuits, vol. 30, pp. 1246-1253, Nov. 1995.
    • (1995) IEEE J. Solid-state Circuits , vol.30 , pp. 1246-1253
    • Dobbelaere, I.1    Horowitz, M.2    Elgamal, A.3
  • 23
    • 0030193282 scopus 로고    scopus 로고
    • Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI
    • July
    • T. lima, M. Mizuno, T. Horiuchi, and M. Yamashina, "Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI," IEEE Trans. Electron Devices, vol. 79, pp. 942-947, July 1996.
    • (1996) IEEE Trans. Electron Devices , vol.79 , pp. 942-947
    • Lima, T.1    Mizuno, M.2    Horiuchi, T.3    Yamashina, M.4
  • 26
    • 0026141225 scopus 로고
    • Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAMs
    • E. Seevinck, P. J. van Beers, and H. Ontrop, "Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAMs," IEEE J. Solid-State Circuits, pp. 525-536, 1991.
    • (1991) IEEE J. Solid-state Circuits , pp. 525-536
    • Seevinck, E.1    Van Beers, P.J.2    Ontrop, H.3
  • 27
    • 0030121501 scopus 로고    scopus 로고
    • A current direction sense technique for multiport SRAMs
    • Apr.
    • M. Izumikawa and M. Yamashina, "A current direction sense technique for multiport SRAMs," IEEE J. Solid-State Circuits, pp. 546-551, Apr. 1996.
    • (1996) IEEE J. Solid-state Circuits , pp. 546-551
    • Izumikawa, M.1    Yamashina, M.2
  • 31
    • 0026853678 scopus 로고
    • A high speed sensing scheme for IT dynamic RAMs utilizing the clamped bit-line sense amplifier
    • Apr.
    • T. N. Blalock and R. C. Jaeger, "A high speed sensing scheme for IT dynamic RAMs utilizing the clamped bit-line sense amplifier," IEEE J. Solid-State Circuits, vol. 27, pp. 618-625, Apr. 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , pp. 618-625
    • Blalock, T.N.1    Jaeger, R.C.2
  • 32
    • 84964422417 scopus 로고    scopus 로고
    • Current-sensing techniques for global interconnects in Very Deep Submicron (VDSM) CMOS
    • A. Maheshwari and W. Burleson, "Current-sensing techniques for global interconnects in Very Deep Submicron (VDSM) CMOS," in Proc. IEEE Computer Society Workshop VLSI, 2001, pp. 66-70.
    • (2001) Proc. IEEE Computer Society Workshop VLSI , pp. 66-70
    • Maheshwari, A.1    Burleson, W.2
  • 33
    • 12344293184 scopus 로고    scopus 로고
    • Current-sensing for global interconnects, secondary design issues: Analysis and solutions
    • _, "Current-sensing for global interconnects, secondary design issues: Analysis and solutions," in Proc. Int. Workshop Power and Timing Modeling, Optimization, and Simulation, 2001, pp. 4.4.1-4.4.10.
    • (2001) Proc. Int. Workshop Power and Timing Modeling, Optimization, and Simulation
  • 35
    • 0036045345 scopus 로고    scopus 로고
    • Delay and power model for current-mode signaling in deep submicron global interconnects
    • R. Bashirullah, W. Liu, and R. Cavin III, "Delay and power model for current-mode signaling in deep submicron global interconnects," in Proc. Custom Integrated Circuit Conf, 2002, pp. 513-516.
    • (2002) Proc. Custom Integrated Circuit Conf , pp. 513-516
    • Bashirullah, R.1    Liu, W.2    Cavin III, R.3
  • 36
    • 0027150940 scopus 로고
    • FASTHENRY: A multipole-accelerated 3-D inductance extraction program
    • M. Kamon, M. Tsuk, and J. White, "FASTHENRY: A multipole-accelerated 3-D inductance extraction program," in Proc. IEEE Design Automation Conf, 1993, pp. 678-683.
    • (1993) Proc. IEEE Design Automation Conf , pp. 678-683
    • Kamon, M.1    Tsuk, M.2    White, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.