Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI

IEICE Transactions on Electronics

Volumn E79-C, Issue 7, 1996, Pages 942-947

  Iima, Tomofumi ^b   Mizuno, Masayuki ^a,b   Horiuchi, Tadahiko ^b   Yamashina, Masakazu ^a,b  

^a IEEE

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; SCHEMATIC DIAGRAMS; SIGNAL RECEIVERS; ULSI CIRCUITS;

INTERCONNECT DELAY; TRANSIENT SENSITIVE ACCELERATOR;

TRIGGER CIRCUITS;

EID: 0030193282     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (4)

1. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
2. T. Sakurai and K. Tamaru, "Simple formulas for two- and three-dimensional capacitances," IEEE Trans. Electron Devices, vol. ED-30, no. 2, pp. 183-185, Feb. 1983.
3. T. Sakurai, "Approximation of wiring delay in MOSFET LSI," IEEE J. Solid-State Circuits, vol. SC-18, no. 4, pp. 418-425, Aug. 1983.
4. T. Iima, M. Mizuno, T. Horiuchi, and M. Yamashina, "Capacitance coupling immune, transient sensitive accelerator for resistive interconnection signals of sub-quarter micron ULSI," in Symp. on VLSI Circuits Dig. of Tech. Papers, 1995, pp. 31-32.