메뉴 건너뛰기




Volumn , Issue , 2000, Pages 352-376

Techniques for driving interconnect

Author keywords

Capacitance; Conductors; Copper; Inductance; Materials; Resistance

Indexed keywords

COPPER; ELECTRIC CONDUCTORS; ELECTRIC RESISTANCE; INDUCTANCE; MATERIALS;

EID: 0011636607     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/9780470544365.ch17     Document Type: Chapter
Times cited : (4)

References (17)
  • 1
    • 0027844919 scopus 로고
    • Inductance on Silicon for Sub-Micron CMOS VLSI
    • Kyoto, Japan, May
    • D. A. Priore, “Inductance on Silicon for Sub-Micron CMOS VLSI,” Proc. Ieee Symposium on VLSI Circuits, Kyoto, Japan, pp. 17-18, May 1993.
    • (1993) Proc. Ieee Symposium on VLSI Circuits , pp. 17-18
    • Priore, D.A.1
  • 2
    • 0031622746 scopus 로고    scopus 로고
    • Figure of Merit to Characterize the Importance of On-Chip Inductance
    • San Francisco, CA
    • Y. I. Ismael, E. G. Friedman, and J. L. Neves, “Figure of Merit to Characterize the Importance of On-Chip Inductance,” DAC 98, San Francisco, CA, pp. 560-565.
    • DAC 98 , pp. 560-565
    • Ismael, Y.I.1    Friedman, E.G.2    Neves, J.L.3
  • 3
    • 0032683656 scopus 로고    scopus 로고
    • On-chip Inductance Issues in Multiconductor Systems
    • New Orleans, June
    • S. V. Morton, “On-chip Inductance Issues in Multiconductor Systems,” DAC 99, New Orleans, June, pp. 921-926.
    • DAC 99 , pp. 921-926
    • Morton, S.V.1
  • 7
    • 0030697661 scopus 로고    scopus 로고
    • Wire Segmenting for Improved Buffer Insertion
    • ANAHEM, CA, June
    • C. J. Alpert, “Wire Segmenting for Improved Buffer Insertion,” DAC 97, ANAHEM, CA, June 97, pp. 588-593.
    • DAC 97 , vol.97 , pp. 588-593
    • Alpert, C.J.1
  • 8
    • 0030110490 scopus 로고    scopus 로고
    • Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model
    • March
    • J. Lillis, C. K. Cheng and T. Lin, “Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model,” IEEE JSSC, vol. 31, no. 3, pp. 437-446, March 1996.
    • (1996) IEEE JSSC , vol.31 , Issue.3 , pp. 437-446
    • Lillis, J.1    Cheng, C.K.2    Lin, T.3
  • 9
    • 0027575799 scopus 로고
    • Sub-IV Swing Internal Bus Architecture for Future Low-Power ULSIs,”
    • April
    • Y. Nakagome, et al., “Sub-IV Swing Internal Bus Architecture for Future Low-Power ULSI’s,” IEEE JSSC, vol. 28, no. 4, pp. 414-419, April 1993.
    • (1993) IEEE JSSC , vol.28 , Issue.4 , pp. 414-419
    • Nakagome, Y.1
  • 10
    • 0029289214 scopus 로고
    • Data-Dependent Logic Swing Internal Bus Architecture for Ultralow-Power LSIs,”
    • April
    • M. Hiraki, et al., “Data-Dependent Logic Swing Internal Bus Architecture for Ultralow-Power LSI’s,” IEEE JSSC, vol. 30, no. 4, pp. 397-402, April 1995.
    • (1995) IEEE JSSC , vol.30 , Issue.4 , pp. 397-402
    • Hiraki, M.1
  • 11
    • 0030241263 scopus 로고    scopus 로고
    • A Signal-Swing Suppressing Strategy for Power and Layout Area Savings Using Time-Multiplexed Differential Data-Transfer Scheme
    • Sep
    • H. Yamauchi and A. Matsuzawa, “A Signal-Swing Suppressing Strategy for Power and Layout Area Savings Using Time-Multiplexed Differential Data-Transfer Scheme,” IEEE JSSC, vol. 31, no. 9, pp. 1285-1294, Sep. 1996.
    • (1996) IEEE JSSC , vol.31 , Issue.9 , pp. 1285-1294
    • Yamauchi, H.1    Matsuzawa, A.2
  • 12
    • 0002581863 scopus 로고    scopus 로고
    • Low-Power Design of High-Capacitive CMOS Circuits Using a New Charge Sharing Scheme
    • Feb
    • M. M. Khellah and M. I. Elmasry, “Low-Power Design of High-Capacitive CMOS Circuits Using a New Charge Sharing Scheme,” IEEE ISSCC, vol. 42, pp. 286-287, Feb. 1999.
    • (1999) IEEE ISSCC , vol.42 , pp. 286-287
    • Khellah, M.M.1    Elmasry, M.I.2
  • 13
    • 85036628375 scopus 로고    scopus 로고
    • National Technology Roadmap for Semiconductors
    • “National Technology Roadmap for Semiconductors,” pp. 99-113, SI A 97 Edition.
    • SI a 97 Edition , pp. 99-113
  • 14
    • 35048834531 scopus 로고
    • Bus-Invert Coding for Low-Power I/O
    • March
    • M. R. Stan and W. P. Burleson, “Bus-Invert Coding for Low-Power I/O,” IEEE Transactions on VLSI Systems, vol. 3, no. 1, pp. 49-58, March 1995.
    • (1995) IEEE Transactions on VLSI Systems , vol.3 , Issue.1 , pp. 49-58
    • Stan, M.R.1    Burleson, W.P.2
  • 15
    • 84882356591 scopus 로고
    • Optimal Methods of Driving Interconnections in VLSI Circuits
    • May
    • M. Nekili and Y. Savaria, “Optimal Methods of Driving Interconnections in VLSI Circuits,” Proc. Ieee ISCAS, pp. 21-24, May 1992.
    • (1992) Proc. Ieee ISCAS , pp. 21-24
    • Nekili, M.1    Savaria, Y.2
  • 16
    • 0027259927 scopus 로고
    • Parallel Regeneration of Interconnections in VLSI & ULSI Circuits
    • May
    • M. Nekili and Y. Savaria, “Parallel Regeneration of Interconnections in VLSI & ULSI Circuits,” Proc. Ieee ISCAS, pp. 2023-2026, May 1993.
    • (1993) Proc. Ieee ISCAS , pp. 2023-2026
    • Nekili, M.1    Savaria, Y.2
  • 17
    • 0030121501 scopus 로고    scopus 로고
    • A Current Direction Sense Technique for Multiport SRAM’s
    • April
    • M. Izumikawa and M. Yamashina, “A Current Direction Sense Technique for Multiport SRAM’s,” IEEE JSSC, vol 31, no. 4, April 1996.
    • (1996) IEEE JSSC , vol.31 , Issue.4
    • Izumikawa, M.1    Yamashina, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.