High performance double-gate device technology challenges and opportunities

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 492-495

  Ieong, M ^a   Wong, H S P ^c   Nowak, E ^b   Kedzierski, J ^c   Jones, E C ^c  

^a IBM RESEARCH   (United States)

^b IBM MICROELECTRONICS   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

CMOS technology; Dielectrics; Doping; Double gate FETs; Fabrication; Microelectronics; Research and development; Silicon; Threshold voltage; Transistors

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; DOPING (ADDITIVES); FABRICATION; FIELD EFFECT TRANSISTORS; MICROELECTRONICS; MIXED SIGNAL INTEGRATED CIRCUITS; SILICON; THRESHOLD VOLTAGE; TRANSISTORS;

CMOS TECHNOLOGY; DEVICE INTEGRATION; DOUBLE-GATE DEVICE; DOUBLE-GATE FETS; EXTRINSIC RESISTANCES; MIXED SIGNAL APPLICATIONS; RESEARCH AND DEVELOPMENT; ULTRA-LOW-VOLTAGE;

GATE DIELECTRICS;

EID: 10844274151     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996793     Document Type: Conference Paper

References (6)

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2. H.-S. P. Wong et al., "Nanoscale CMOS," IEEE Proceedings, p. 537, April 1999.
3. H.-S. Wong, K. Chan, and Y. Taur, "Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel," International Electron Devices Meeting, p. 427,1997.
4. M. Ieong et al., "Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs," 2001 International Electron Device Meeting.
5. Ieong et al., "DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS," Simulation of Semiconductor Processes and Devices (SISPAD), pp. 147-150, 2000.
6. J. Kedzierski et al, "High-Performance Symmetric-Gate and CMOS-Compatible Vt asymmetric-gate FinFET Devices," 2001. International Electron Devices Meeting..