Channeled-BSG: A universal floorplan for simultaneous place/route with IC applications

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages 418-425

  Nakatake, Shigetoshi ^a   Sakanushi, Keishi ^a   Kajitani, Yoji ^a   Kawakita, Masahiro ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS; MATHEMATICAL MODELS; SIMULATED ANNEALING;

BOUNDED-SLICELINE-GRID (BSG) STRUCTURE;

DATA STRUCTURES;

EID: 0032320385     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)