-
1
-
-
0009554967
-
Covering the square by squares without overlapping
-
in Japanese
-
M. Abe, "Covering the square by squares without overlapping," Journal of Japan Mathematical Physics, Vol. 4, No. 4, pp. 359-366, 1930 (in Japanese).
-
(1930)
Journal of Japan Mathematical Physics
, vol.4
, Issue.4
, pp. 359-366
-
-
Abe, M.1
-
2
-
-
0033701594
-
B*-Tree: A new representation for non-slicing floorplan
-
Y.-C. Chang, Y. W. Chang, G.-M. Wu, and S. W. Wu, "B*-Tree: A New Representation for Non-Slicing Floorplan," Proc. of 37th DAC, pp. 458-463, 2000.
-
(2000)
Proc. of 37th DAC
, pp. 458-463
-
-
Chang, Y.-C.1
Chang, Y.W.2
Wu, G.-M.3
Wu, S.W.4
-
3
-
-
0032003077
-
A Unified approach to topology generation and optimal sizing of floorplans
-
P. S. Dasgupta, S. Sur-Kolay, and B. B. Bhattacharya, "A Unified Approach to Topology Generation and Optimal Sizing of Floorplans, Trans. on CAD, Vol. 17, No.2, pp. 126-1335, 1998.
-
(1998)
Trans. on CAD
, vol.17
, Issue.2
, pp. 126-1335
-
-
Dasgupta, P.S.1
Sur-Kolay, S.2
Bhattacharya, B.B.3
-
4
-
-
0032690067
-
An o-tree representation of non-slicing floorplan and its applications
-
P. N. Guo, C. K. Cheng, and T. Yoshimura, "An O-Tree Representation of Non-Slicing Floorplan and Its Applications," Proc. 36th DAC, pp. 268-273, 1999.
-
(1999)
Proc. 36th DAC
, pp. 268-273
-
-
Guo, P.N.1
Cheng, C.K.2
Yoshimura, T.3
-
5
-
-
0034481271
-
Corner block list: An efficient topological representation of non-slicing floorplan
-
2000
-
X. Hong, S. Dong, Y. Ma, Y. Cai, C.-K. Cheng, and J. Gu, "Corner Block List: An efficient topological representation of Non-Slicing floorplan," Proc. of ICCAD 2000, pp. 8-12, 2000.
-
(2000)
Proc. of ICCAD
, pp. 8-12
-
-
Hong, X.1
Dong, S.2
Ma, Y.3
Cai, Y.4
Cheng, C.-K.5
Gu, J.6
-
6
-
-
13444305734
-
Selected sequence-pair
-
in Japanese
-
C. Kodama and K. Fujiyoshi, "Selected Sequence-Pair," Technical Report of IEICE, VLD2001-17, Vol. 101, No. 46, pp. 65-72, 2001 (in Japanese).
-
(2001)
Technical Report of IEICE, VLD2001-17
, vol.101
, Issue.46
, pp. 65-72
-
-
Kodama, C.1
Fujiyoshi, K.2
-
7
-
-
0030378255
-
VLSI module placement based on rectangle-packing by the sequence-pair
-
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair," Trans. on CAD, Vol. 15, No. 12, pp. 1518-1524, 1996.
-
(1996)
Trans. on CAD
, vol.15
, Issue.12
, pp. 1518-1524
-
-
Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
-
8
-
-
0030703004
-
A mapping from sequence-pair to rectangular dissection
-
H. Murata, K, Fujiyoshi, T. Watanabe, and Y. Kajitani, "A Mapping from Sequence-Pair to Rectangular Dissection," Proc. of ASPDAC 97, pp. 625-633, 1997.
-
(1997)
Proc. of ASPDAC 97
, pp. 625-633
-
-
Murata, K.H.1
Watanabe, F.T.2
Kajitani, Y.3
-
9
-
-
0032090672
-
Module packing based on the bsg-structure and IC layout applications
-
S. Nakatake, H. Murata, K. Fujiyoshi, and Y. Kajitani, "Module Packing Based on the BSG-Structure and IC Layout Applications," Trans. on CAD, Vol. 17, No. 6, pp. 519-530, 1998.
-
(1998)
Trans. on CAD
, vol.17
, Issue.6
, pp. 519-530
-
-
Nakatake, S.1
Murata, H.2
Fujiyoshi, K.3
Kajitani, Y.4
-
10
-
-
85031277343
-
Automatic floorplan design
-
R. H. J. M. Otten, "Automatic floorplan design," Proc. of 19th DAC, pp. 261-267, 1982.
-
(1982)
Proc. of 19th DAC
, pp. 261-267
-
-
Otten, R.H.J.M.1
-
11
-
-
0033704928
-
An enhanced perturbing algorithm for floorplan design using the O-tree representation
-
Y. Pang, C. K. Cheng, and T. Yoshimura, "An Enhanced Perturbing Algorithm for Floorplan Design using the O-Tree Representation," Proc. of ISPD 2000, pp. 168-173, 2000.
-
(2000)
Proc. of ISPD 2000
, pp. 168-173
-
-
Pang, Y.1
Cheng, C.K.2
Yoshimura, T.3
-
12
-
-
0005497664
-
The quarter-state sequence (q-sequence) to represent the floorplan and applications to layout optimization
-
K. Sakanushi and Y. Kajitani, "The Quarter-State Sequence (Q-Sequence) to Represent the Floorplan and Applications to Layout Optimization," Proc. of IEEE Asia Pacific Conference Circuits And Systems 2000, pp. 829-832, 2000.
-
(2000)
Proc. of IEEE Asia Pacific Conference Circuits and Systems 2000
, pp. 829-832
-
-
Sakanushi, K.1
Kajitani, Y.2
-
13
-
-
0013407906
-
A New encoding scheme for rectangle packing problem
-
T. Takahashi, "A New Encoding Scheme for Rectangle Packing Problem," Proc. of ASPDAC 2000, pp. 175-178, 2000.
-
(2000)
Proc. of ASPDAC 2000
, pp. 175-178
-
-
Takahashi, T.1
-
14
-
-
0013354032
-
Linear time decodable rectangular dissection to represent arbitrary packing using q-sequence
-
M. Tsuboi, C. Kodama, K. Fujiyoshi, K. Sakanushi, and A. Takahashi, "Linear Time Decodable Rectangular Dissection to Represent Arbitrary Packing using Q-Sequence," Proc. of The Tenth Workshop on Synthesis And System Integration of MIxed Technologies 2001. pp. 272-278, 2001.
-
(2001)
Proc. of the Tenth Workshop on Synthesis and System Integration of MIxed Technologies 2001
, pp. 272-278
-
-
Tsuboi, M.1
Kodama, C.2
Fujiyoshi, K.3
Sakanushi, K.4
Takahashi, A.5
-
15
-
-
85040657895
-
A new algorithm for floorplan design
-
D. F. Wong and C. L. Liu, "A New Algorithm for Floorplan Design," Proc. of 23rd DAC, pp. 101-107, 1986.
-
(1986)
Proc. of 23rd DAC
, pp. 101-107
-
-
Wong, D.F.1
Liu, C.L.2
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