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Volumn 151, Issue 6, 2004, Pages 457-465

REMcode: Relocating embedded code for improving system efficiency

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CACHE MEMORY; CODES (SYMBOLS); HEURISTIC METHODS; HIERARCHICAL SYSTEMS; SEMANTICS; STORAGE ALLOCATION (COMPUTER);

EID: 11244289384     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20040942     Document Type: Article
Times cited : (6)

References (33)
  • 2
    • 0036917239 scopus 로고    scopus 로고
    • 'Synthesis of customized loop caches for core-based embedded systems'
    • Presented at
    • Cotterell, S., and Vahid, F.: 'Synthesis of customized loop caches for core-based embedded systems'. Presented at Int. Conf. on CAD, 2002
    • (2002) Int. Conf. on CAD
    • Cotterell, S.1    Vahid, F.2
  • 3
    • 0036045884 scopus 로고    scopus 로고
    • 'Scratchpad memory: A design alternative for cache on-chip memory in embedded systems'
    • Banakar, R., Steinke, S., Lee, B.S., Balakrishnan, M., and Marwedel, P.: 'Scratchpad memory: a design alternative for cache on-chip memory in embedded systems'. Proc. CODES, 2002, pp. 73-78
    • (2002) Proc. CODES , pp. 73-78
    • Banakar, R.1    Steinke, S.2    Lee, B.S.3    Balakrishnan, M.4    Marwedel, P.5
  • 5
    • 0031619877 scopus 로고    scopus 로고
    • 'Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors'
    • Bellas, N., Hajj, I., Polychronopoulos, C., and Stamoulis, G.: 'Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors'. Proc. ISLPED, 1998, pp. 70-75
    • (1998) Proc. ISLPED , pp. 70-75
    • Bellas, N.1    Hajj, I.2    Polychronopoulos, C.3    Stamoulis, G.4
  • 7
    • 11244334873 scopus 로고    scopus 로고
    • 'Reducing power with an 10 instruction cache using history-based prediction'
    • Presented at
    • Wang, W., Veidenbaum, A.V., and Nicolau, A.: 'Reducing power with an 10 instruction cache using history-based prediction'. Presented at IWIA, 2002
    • (2002) IWIA
    • Wang, W.1    Veidenbaum, A.V.2    Nicolau, A.3
  • 8
  • 11
    • 0026157612 scopus 로고
    • 'IMPACT: An architectural framework for multiple-instruction-issue processors'
    • Chang, P.P., Mahlke, S.A., Chen, W.Y., Warter, N.J., and Hwu, W.W.: 'IMPACT: an architectural framework for multiple-instruction-issue processors', Comput. Arch. News, 1991, vol. 19
    • (1991) Comput. Arch. News , vol.19
    • Chang, P.P.1    Mahlke, S.A.2    Chen, W.Y.3    Warter, N.J.4    Hwu, W.W.5
  • 12
    • 0006917147 scopus 로고
    • 'A portable machine-independent global optimizer - Design and measurement'
    • PhD thesis, Computer Systems Lab, Stanford Univ
    • Chow, F.: 'A portable machine-independent global optimizer - design and measurement'. PhD thesis, Computer Systems Lab, Stanford Univ., 1983
    • (1983)
    • Chow, F.1
  • 15
    • 84976682502 scopus 로고
    • 'Procedure merging with instruction caches'
    • McFarling, S.: 'Procedure merging with instruction caches', SIGPLAN Not., 1991, 26, p. 71
    • (1991) SIGPLAN Not. , vol.26 , pp. 71
    • McFarling, S.1
  • 16
    • 0035208466 scopus 로고    scopus 로고
    • 'I-CoPES: Fast instruction code placement for embedded systems to improve performance and energy efficiency'
    • Parameswaran, S., and Henkel, J.: 'I-CoPES: fast instruction code placement for embedded systems to improve performance and energy efficiency'. Proc. Conf. on ICCAD, 2001, pp. 635-641
    • (2001) Proc. Conf. on ICCAD , pp. 635-641
    • Parameswaran, S.1    Henkel, J.2
  • 17
    • 0001324927 scopus 로고    scopus 로고
    • 'Code placement techniques for cache miss rate reduction'
    • Tomiyama, H., and Yasuura, H.: 'Code placement techniques for cache miss rate reduction', ACM Trans. Des. Autom. Electron. Syst., 1997, 2, pp. 410-429
    • (1997) ACM Trans. Des. Autom. Electron. Syst. , vol.2 , pp. 410-429
    • Tomiyama, H.1    Yasuura, H.2
  • 18
    • 22844455988 scopus 로고    scopus 로고
    • 'Performance estimation of embedded software with instruction cache modeling'
    • Li, Y.T., Malik, S., and Wolfe, A.: 'Performance estimation of embedded software with instruction cache modeling', ACM Trans. Des. Autom. Electron. Syst., 1999, 4, pp. 257-279
    • (1999) ACM Trans. Des. Autom. Electron. Syst. , vol.4 , pp. 257-279
    • Li, Y.T.1    Malik, S.2    Wolfe, A.3
  • 20
    • 0024933416 scopus 로고
    • 'SMART (strategic memory allocation for real-time) cache design'
    • Kirk, D.B.: 'SMART (strategic memory allocation for real-time) cache design'. Proc. Symp. on Real-Time Systems, 1989, pp. 229-237
    • (1989) Proc. Symp. on Real-Time Systems , pp. 229-237
    • Kirk, D.B.1
  • 21
    • 84880896550 scopus 로고
    • 'SMART (strategic memory allocation for real-time) cache design using the mips r3000'
    • Kirk, D.B., and Strosnider, J.K.: 'SMART (strategic memory allocation for real-time) cache design using the mips r3000'. Proc. Symp. on 11th Real-Time Systems, 1990, pp. 322-330
    • (1990) Proc. Symp. on 11th Real-Time Systems , pp. 322-330
    • Kirk, D.B.1    Strosnider, J.K.2
  • 22
    • 11244288634 scopus 로고    scopus 로고
    • 'Hardware/software co-synthesis with memory hierarchies'
    • Presented at
    • Yanbing, L., and Wolf, W.: 'Hardware/software co-synthesis with memory hierarchies'. Presented at Conf. on Design Automation, 1998
    • (1998) Conf. on Design Automation
    • Yanbing, L.1    Wolf, W.2
  • 26
    • 0031624030 scopus 로고    scopus 로고
    • 'Power optimisation of variable voltage core-based systems'
    • Hong, I., and Kirovski, D., et al.: 'Power optimisation of variable voltage core-based systems'. Proc. Conf. on Design Automation, 1998, pp. 176-181
    • (1998) Proc. Conf. on Design Automation , pp. 176-181
    • Hong, I.1    Kirovski, D.2
  • 27
    • 84884690219 scopus 로고    scopus 로고
    • 'A hybrid approach for core-based systems-level power modeling'
    • Givargis, T., Vahid, F., and Henkel, J.: 'A hybrid approach for core-based systems-level power modeling'. Proc. ASP-DAC, 1999, pp. 141-145
    • (1999) Proc. ASP-DAC , pp. 141-145
    • Givargis, T.1    Vahid, F.2    Henkel, J.3
  • 28
    • 0032640879 scopus 로고    scopus 로고
    • 'Cycle-accurate simulation of energy consumption in embedded systems'
    • Simunic, T., Benini, L., and De Micheli, G.: 'Cycle-accurate simulation of energy consumption in embedded systems'. Proc. Conf. on Design Automation, 1999, pp. 867-872
    • (1999) Proc. Conf. on Design Automation , pp. 867-872
    • Simunic, T.1    Benini, L.2    De Micheli, G.3
  • 30
    • 0004339859 scopus 로고    scopus 로고
    • 'Warts: Wisconsin architectural research tool set'
    • Computer Science Department, University of Wisconsin
    • Hill, M.D., Larus, J.R., and Lebeck, A.R., et al.: 'Warts:wisconsin architectural research tool set', Computer Science Department, University of Wisconsin, http://www.cs.wisc.edu/~markhill/ DineroIV/
    • Hill, M.D.1    Larus, J.R.2    Lebeck, A.R.3
  • 31
    • 12344315233 scopus 로고    scopus 로고
    • Dinero iv trace-driven uniprocessor cache simulator
    • Computer Science Department, University of Wisconsin
    • Edler, J., and Hill, M.D.: Dinero iv trace-driven uniprocessor cache simulator. Computer Science Department, University of Wisconsin
    • Edler, J.1    Hill, M.D.2
  • 32
    • 0031634246 scopus 로고    scopus 로고
    • 'A framework for estimating and minimizing energy dissipation of embedded hw/sw systems'
    • Li, Y., and Henkel, J.: 'A framework for estimating and minimizing energy dissipation of embedded hw/sw systems'. Proc. Design Automation Conf., 1998, pp. 188-193
    • (1998) Proc. Design Automation Conf. , pp. 188-193
    • Li, Y.1    Henkel, J.2
  • 33
    • 0003450887 scopus 로고    scopus 로고
    • Cacti 3.0: An integrated cache timing, power, and area model
    • August
    • Shivakumar, P., and Jouppi, N.P.: Cacti 3.0: An integrated cache timing, power, and area model. Compaq WRL Report, August 2001
    • (2001) Compaq WRL Report
    • Shivakumar, P.1    Jouppi, N.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.