Energy benefits of a configurable line size cache for embedded systems

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2003-January, Issue , 2003, Pages 87-91

  Zhang, Chuanjun ^a   Vahid, Frank ^a,b   Najjar, Walid ^a  

^a University of California Riverside   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Batteries; Computer science; Embedded computing; Embedded system; Energy consumption; Microprocessors; National electric code; Power engineering and energy; Switches; Wires

Indexed keywords

CACHE MEMORY; COMPUTER SCIENCE; ELECTRIC SWITCHES; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; SOLAR CELLS; SWITCHES; SYSTEMS ANALYSIS; WIRE;

EMBEDDED COMPUTING; EMBEDDED MICROPROCESSORS; ENERGY BENEFITS; ENERGY IMPACT; IMPACT PERFORMANCE; MEMORY ACCESS; NATIONAL ELECTRIC CODE; POWER ENGINEERING AND ENERGIES;

EMBEDDED SYSTEMS;

EID: 84942058694     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2003.1183357     Document Type: Conference Paper

References (18)

1. L.Benini, G. De Micheli, E. Macii, D.Scjuto, C.Silvano. "Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems," GLS-VLSI-97:IEEE 7th Great Lake Symposium on VLSI.pp.77-82:Urbana-Champaign:IL:March 1997.
2. D. Burger and T.M. Austin. The SimpleScalar Tool Set, Version 2.0. University of Wisconsin-Madison Computer Sciences Department Technical Repor #1342. June, 1997
3. J. L. Hennessy and D .A. Patterson: Computer architecture Quantitative Approach, 2nd Edition, Morgan-Kaufmann Publishing Co., Menlo Park, CA.1996
4. http://www.mips.com
5. http://www.specbench.org/osg/cpu2000/
6. K. Inoue, K. Kai, A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size, IEICE Trans. Electron. Vol. E83-CV No.11, Nov. 2000
7. C. Lee, M. Potkonjak and W. Mangione-Smith. MediaBench C. Lee, M. Potkonjak and W. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems, MICRO 1997
8. L. Lee., B. Moyer, J. Arends. Low-Cost Embedded Program Loop Caching - Revisited. University of Michigan Technical Report CSE-TR-411-99, 1999.Applications. International Symposium on System-Level Synthesis, pp. 74-81, 1997.
9. A. Malik, B. Moyer and D. Cermak. "A Low Power Unified Cache Architecture Providing Power and Performance Flexibility." International Symposium on Low Power Electronics and Design. June. 2000.
10. D. Nicolaescu, X. Ji, A. Veidenbaum, A. Nicolau and R. Gupta, "Compiler-directed Cache Line Size Adaptivity", IMS, 2000.
11. Glen Reinman and Norman P .Jouppi, CACTI 2.0:An Integrated Cache Timing and Power Model. WRL Research Report 2000/7
12. Simon Segars, Low Power Design Techniques for Microprocessors. ISSCC2001
13. M. R. Stan, W. P. Burleson, "Bus-Invert Coding for Low-Power I/O," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 1, pp. 49-58, March 1995
14. F. Vahid and T. Givargis. Platform Tuning for Embedded Systems Design. IEEE Computer, Vol. 34, No. 3, pp. 112-114, March 2001.
15. A. Veidenbaum, W. Tang, R. Gupta, "Adapting Cache Line Size to Application Behavior. "ICS'99 Rhodes Greece
16. N.H.E. Weste and K.Eshraghian, "Principles of CMOS VLSI Design, A System Perspective" Second Edition. Addison-Wesley. 1993 pp. 233-235.
17. E. Witchel and K. Asannovic, "The Span Cache: Software Controlled Tag Checks and Cache Line Size", 28th ISCA, Sweden, 2001
18. Semiconductor Industry Association. International Technology Roadmap for Semiconductors: 1999 edition. Austin, TX: International SEMATECH, 1999.