A power-configurable bus for embedded systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Zhang, Chuanjun ^a   Vahid, Frank ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Architecture tuning; Bus; Configurable systems; Low power; Platforms; System on a chip

Indexed keywords

BENCHMARKING; CACHE MEMORY; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS;

POWER CONFIGURABLE BUS; SYSTEM ON A CHIP;

EMBEDDED SYSTEMS;

EID: 0036291197     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Selective cache ways: On-demand cache resource allocation
2. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
3. Exploiting fixed programs in embedded systems: A loop cache example
4. A low power unified cache architecture providing power and performance flexibility
5. A low power unified cache architecture providing power and performance flexibility
6. Comparison of wafer scale integration with VLSI packaging approaches
7. Bus-invert coding for low-power I/O
8. Platform tuning for embedded systems design