Power savings in embedded processors through decode filter cache

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 443-448

  Tang, Weiyu ^a   Gupta, Rajesh ^a   Nicolau, Alexandru ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED PROCESSORS; INSTRUCTION CACHES; INSTRUCTION FETCH; INSTRUCTION STREAMS; PERFORMANCE DEGRADATION; POWER SAVINGS; PREDICTION MECHANISMS; PROCESSOR POWER;

CACHE MEMORY; EXHIBITIONS;

DESIGN;

EID: 1642306627     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998311     Document Type: Conference Paper

References (14)

1. T. Anderson and S. Agarwala. Effective hardware-based two-way loop cache for high performance low power processors. In IEEE Int'l Conf. on Computer Design, pages 403-407, 2000.
2. N. Bellas, I. Hajj, and C. Polychronopoulos. Using dynamic cache management techniques to reduce energy in a highperformance processor. In Int'l Symp. on Low Power Electronics and Design, pages 64-69, 1999.
3. D. Burger and T.Austin. The simplescalar toolset, version 2.0. Technical Report TR-97-1342, University of Wisconsin-Madison, 1997.
4. K. Ghose and M. Kamble. Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation. In Int'l Symp. on Low Power Electronics and Design, pages 70-75, 1999.
5. J. Montanaro et al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE Journal of Solid-State Circuits, 32(11):1703-14, 1996.
6. J. Kin, M. Gupta, andW. Mangione-Smith. The filter cache: An energy efficient memory structure. In Int'l Symp. Microarchitecture, pages 184-193, 1997.
7. C. Lee, M. Potkonjak, and W. Mangione-Smith. Mediabench: a tool for evaluating and synthesizing multimedia and communicatons systems. In Int'l Symp. Microarchitecture, pages 330-335, 1997.
8. S. Manne, A. Klauser, and D. Grunwald. Pipeline gating: speculation control for energy reduction. In Int'l Symp. Computer Architecture, pages 132-141, 1998.
9. A. Seznec. Decoupled sectored caches: conciliating low tag implementation cost. In Int'l Symp. Computer Architecture, pages 384-393, 1994.
10. B. Solomon, A. Mendelson, D. Orenstein, Y. Almog, and R. Ronen. Micro-operation cache: a power aware frontend for the variable instruction length isa. In Int'l Symp. on Low Power Electronics and Design, pages 4-9, 2001.
11. E. Talpes and D. Marculescu. Power reduction through work reuse. In Int'l Symp. on Low Power Electronics and Design, pages 340-345, 2001.
12. W. Tang, R. Gupta, and A. Nicolau. Design of a predictive filter cache for energy savings in high performance processor architectures. In Int'l Conf. on Computer Design, 2001.
13. S.Wilton and N. Jouppi. An enhanced access and cycle time model for on-chip caches. Technical Report 93/5, Digital Western Research Laboratory, 1994.
14. T.-Y. Yeh, D. Marr, and Y. Patt. Increasing the instruction fetch rate via multiple branch prediction and a branch address cache. In Int'l Symp. Computer Architecture, pages 67-76, 1993.