Synthesis of customized loop caches for core-based embedded systems

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 655-662

  Cotterell, Susan ^a   Vahid, Frank ^b  

^a University of California Riverside   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Architecture tuning; Customized architectures; Embedded systems; Estimation; Instruction fetching; Loop cache; Low energy; Low power; Memory hierarchy; Synthesis; Tuning

Indexed keywords

ARCHITECTURE TUNING; CUSTOMIZED ARCHITECTURES; INSTRUCTION FETCHING; INSTRUCTION MEMORY HIERARCHY; LOOP CACHE; MICROPROCESSOR CORES;

CACHE MEMORY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036917239     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774669     Document Type: Conference Paper

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