A BIST Pattern Generator Design for Near-Perfect Fault Coverage

IEEE Transactions on Computers

Volumn 52, Issue 12, 2003, Pages 1543-1558

  Chatterjee, Mitrajit ^a   Pradhan, Dhiraj K ^b  

^a INTEGRATED DEVICE TECHNOLOGY INC   (United States)

^b UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

Built in self test; Core logic; Fault coverage; Linear feedback shift registers; Scan; SOC; Synthesis; Test pattern generation

Indexed keywords

PATTERN GENERATORS;

EMBEDDED SYSTEMS; FORMAL LOGIC; LOGIC GATES; MAPPING; MICROPROCESSOR CHIPS; PRODUCT DESIGN; SHIFT REGISTERS; VECTORS;

BUILT-IN SELF TEST;

EID: 0347380868     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1252851     Document Type: Article

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