Bit-fixing in pseudorandom sequences for scan BIST

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 4, 2001, Pages 545-555

  Touba, Nur A ^a,b   McCluskey, Edward J ^a,c  

^a IEEE   (United States)

^b The University of Texas at Austin   (United States)

^c Stanford University   (United States)

Author keywords

Design for testability; Digital system testing; Logic circuit testing; Self testing; Sequences

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; DIGITAL SYSTEM TESTING; LINEAR FEEDBACK SHIFT REGISTER; LOGIC CIRCUIT TESTING; PSEUDORANDOM SEQUENCES; RANDOM PATTERN RESISTANT FAULTS; SCAN BUILT-IN SELF TEST;

COMPUTER AIDED LOGIC DESIGN; CORRELATION METHODS; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; FEEDBACK; INTEGRATED CIRCUIT TESTING; LINEAR INTEGRATED CIRCUITS; RANDOM PROCESSES; SHIFT REGISTERS;

BUILT-IN SELF TEST;

EID: 0035309368     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.918212     Document Type: Article

References (34)