Test structure verification of logical BIST: Problems and solutions

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 123-130

  Cogswell, Michael ^a   Pearl, Don ^a   Sage, James ^a   Troidl, Alan ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; DESIGN FOR TESTABILITY; POLYNOMIALS; SHIFT REGISTERS;

LINEAR FEEDBACK SHIFT REGISTERS; MULTIPLE INPUT SIGNATURE REGISTER; PSEUDO RANDOM PATTERN GENERATOR; TEST STRUCTURE VERIFICATION;

BUILT-IN SELF TEST;

EID: 0034479267     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2000.894199     Document Type: Article

References (8)

1. N. A. Touba E. J. McCluskey Altering a pseudorandom bit sequence for scan-based BIST Proc. Int. Test Conf. 167 175 Proc. Int. Test Conf. 1996
2. J. Rajski N. Tamarapalli J. Tyszer Automatic synthesis of large phase-shifters for BIST Proc. Int. Test Conf. 1047 1056 Proc. Int. Test Conf. 1998
3. B. L. Keller T. J. Snethen Built-in self-test support in the IBM engineering design system IBM J. Res. Dev. 34 406 415 MARCH 1990
4. G. Hetherington Logic BIST for large industrial designs: Real issues and case studies Proc. Int. Test Conf. 358 367 Proc. Int. Test Conf. 1999