BETSY: Synthesizing circuits for a specified BIST environment

IEEE International Test Conference (TC)

Volumn , Issue , 1998, Pages 144-153

  Zhao, Zhe ^a   Pouya, Bahram ^a   Touba, Nur A ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TEST PATTERN GENERATORS; TIMING CONSTRAINTS;

BUILT-IN SELF TEST; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PROBABILITY; PROBLEM SOLVING; RANDOM PROCESSES;

INTEGRATED CIRCUIT TESTING;

EID: 0032319675     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.1998.743147     Document Type: Conference Paper

References (14)