LOT: Logic Optimization with Testability-New Transformations for Logic Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 5, 1998, Pages 386-399

  Chatterjee, Mitrajit ^a,b   Pradhan, Dhiraj K ^a,c   Kunz, Wolfgang ^a,d  

^a IEEE   (United States)

^b INTEGRATED DEVICE TECHNOLOGY INC   (United States)

^c Stanford University   (United States)

^d GOETHE UNIVERSITY   (Germany)

Author keywords

ATPG; Built in self test; Logic synthesis; Optimization; Testability

Indexed keywords

INTEGRATED CIRCUIT TESTING; LOGIC GATES; OPTIMIZATION;

AUTOMATIC TEST PATTERN GENERATORS (ATPG); REED-MULLER EXPANSIONS;

LOGIC CIRCUITS;

EID: 0032066596     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.703921     Document Type: Article

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