Fully Silicided NiSi and Germanided NiGe Dual Gates on SiO 2 n- and p-MOSFETs

IEEE Electron Device Letters

Volumn 24, Issue 12, 2003, Pages 739-741

  Yu, D S ^a   Wu, C H ^a   Huang, C H ^a   Chin, Albert ^a   Chen, W J ^b   Zhu, Chunxiang ^c   Li, M F ^c   Kwong, Dim Lee ^d  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL FORMOSA UNIVERSITY   (Taiwan)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^d The University of Texas at Austin   (United States)

Author keywords

MOSFET; NiGe; NiSi

Indexed keywords

ELECTRON FILLING LEVELS;

CAPACITANCE; DIELECTRIC MATERIALS; ELECTRIC POTENTIAL; ELECTRON DIFFRACTION; ELECTRON MOBILITY; GATES (TRANSISTOR); HOLE MOBILITY; LEAKAGE CURRENTS; NICKEL COMPOUNDS; SEMICONDUCTOR GROWTH; SILICA; SILICON WAFERS;

MOSFET DEVICES;

EID: 0347131291     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.819274     Document Type: Article

References (17)

1. 2 MOSFET's," IEDM Tech. Dig., pp. 659-662, 2001.
2. 2 CMOS transistors with high quality CVD TaN gate electrode, " in Proc. Symp. VLSI Technology, 2002, pp. 82-83.
3. it," in Proc. Symp. VLSI Technology, 1999, pp. 135-136.
4. 3 gate dielectrics with equivalent oxide thickness 5-10Å," in Proc. Symp. VLSI Technology, 2000, pp. 16-17.
5. 3 suprelattice tunnel diode," in IEDM Tech. Dig., 2001, pp. 171-174.
6. Q. Xiang, J. S. Goo, J. Pan, B. Yu, S. Ahmed, J. Zhang, and M.-R. Lin, "Strained silicon NMOS with nickel-suicide metal gate," in Proc. Symp. VLSI Technology, 2003, pp. 103-104.
7. 3 gate dielectrics," in Proc. Symp. VLSI Technology, 2003, pp. 119-120.
8. Y. C. Yeo, P. Ranade, Q. Lu, R. Lin, T. J. King, and C. Hu, "Effects of high K dielectrics on the workfunctions of metal and silicon gates," in Proc. Symp. VLSI Technology, 2001, pp. 49-50.
9. I. Polishchuk, P. Ranade, T. J. King, and C. Hu, "Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion," IEEE Electron Device Lett., vol. 23, pp. 200-202, Apr. 2002.
10. H. Zhong, S. N. Hong, Y. S. Suh, H. Lazar, G. Heuss, and V. Misra, "Properties of Ru-Ta alloys as gate electrodes for NMOS and PMOS silicon devices," in IEDM Tech. Dig., 2001, pp. 467-470.
11. 2) polysilicon: A novel approach to very low-resistive gate (∼ 2Ω/□) without metal CMP nor etching," in IEDM Tech. Dig., 2001, pp. 815-828.
12. W. P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, and M.-R. Lin, "Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates," in IEDM Tech. Dig., 2002, pp. 367-370.
13. J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, and W. Haensch, "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation," in IEDM Tech. Dig., 2002, pp. 247-250.
14. Z. Krivokapic, W. Maszara, K. Achutan, P. King, J. Gray, M. Sidorow, E. Zhao, J. Zhang, J. Chan, A. Marathe, and M.-R. Lin, "Nickel suicide metal gate FDSOI devices with improved gate oxide leakage," in IEDM Tech. Dig., 2002, pp. 271-274.
15. 3 MOSFETs," IEEE Electron Device Lett., vol. 24, pp. 348-350, May 2003.
16. Y. H. Lin, F. M. Pan, Y. C. Liao, Y. C. Chen, I. J. Hsieh, and A. Chin, "The Cu contamination effect in oxynitride gate dielectrics," J. Electrochem. Soc., vol. 148, no. 4, pp. G627-G629, 2001.
17. 0.7/Si," IEEE Electron Device Lett., vol. 23, pp. 464-466, Aug. 2002.