An effective BIST architecture for fast multiplier cores

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 117-121

  Paschalis, A ^a   Gizopoulos, D ^b   Kranitis, N ^a   Psarakis, M ^a   Zorian, Y ^c  

^a INSTITUTE OF INFORMATICS AND TELECOMMUNICATIONS   (Greece)

^b PLUS Technologies   (Greece)

^c LogicVision Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY COUNTERS; BIST ARCHITECTURES; BOOTH ENCODING; DATA-PATH ARCHITECTURE; FAST MULTIPLIERS; FAULT COVERAGES; MODULE GENERATOR; TEST PATTERN GENERATOR;

DESIGN; ELECTRIC CONVERTERS; EXHIBITIONS;

MULTIPLYING CIRCUITS;

EID: 0000934719     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761106     Document Type: Conference Paper

References (13)

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