An effective built-in self-test scheme for parallel multipliers

IEEE Transactions on Computers

Volumn 48, Issue 9, 1999, Pages 936-950

  Gizopoulos, Dimitris ^a,b   Paschalis, Antonis ^a,c   Zorian, Yervant ^a,d  

^a IEEE   (Greece)

^b 4Plus Technologies SA   (Greece)

^c UNIVERSITY OF ATHENS   (Greece)

^d LogicVision Inc   (United States)

Author keywords

Array multipliers; Built in self test; Cell fault model; Tree multipliers

Indexed keywords

COMPUTATIONAL COMPLEXITY; EMBEDDED SYSTEMS; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS; MULTIPLYING CIRCUITS; PARALLEL PROCESSING SYSTEMS; VECTORS; VLSI CIRCUITS;

ARRAY MULTIPLIERS; CELLULAR FAULT MODEL; ITERATIVE LOGIC ARRAYS; PARALLEL MULTIPLIERS; TREE MULTIPLIERS;

BUILT-IN SELF TEST;

EID: 0033350972     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.795222     Document Type: Article

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