Hierarchical test generation under architectural level functional constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 9, 1996, Pages 1144-1151

  Lee, Jaushin ^a   Patel, Janak H ^a  

^a HEWLETT PACKARD ENTERPRISE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; CONSTRAINT THEORY; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT TESTING; PARAMETER ESTIMATION; VECTORS;

ARCHITECTURAL LEVEL FUNCTIONAL CONSTRAINTS; AUTOMATED TEST PATTERN GENERATION (ATPG); SOFTWARE PACKAGE ARTEST; TEST CUBE JUSTIFICATION TECHNIQUES; VALID CONTROL CODE ABSTRACTION;

SEQUENTIAL CIRCUITS;

EID: 0030245490     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.536720     Document Type: Article

References (22)

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