Low-energy BIST design for scan-based logic circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 546-551

  Bhattacharya, Bhargab B ^a,b   Seth, Sharad C ^a   Zhang, Sheng ^a  

^a UNIVERSITY OF NEBRASKA LINCOLN   (United States)

^b INDIAN STATISTICAL INSTITUTE   (India)

Author keywords

Benchmark testing; Built in self test; Circuit faults; Circuit testing; Energy consumption; Heating; Logic circuits; Logic design; Test pattern generators; Very large scale integration

Indexed keywords

BUILT-IN SELF TEST; DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; ENERGY CONSERVATION; ENERGY UTILIZATION; HEATING; INTEGRATED CIRCUIT TESTING; INTEGRATION TESTING; LOGIC DESIGN; LOW POWER ELECTRONICS; SYSTEMS ANALYSIS; VLSI CIRCUITS;

BENCHMARK CIRCUIT; BENCHMARK TESTING; CIRCUIT FAULTS; CIRCUIT TESTING; RANDOM SWITCHING; STATE TRANSITIONS; TEST APPLICATION TIME; TEST PATTERN GENERATOR;

LOGIC CIRCUITS;

EID: 0142236965     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183191     Document Type: Conference Paper

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