Design for consecutive transparency of cores in system-on-a-chip

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 287-292

  Yoneda, T ^a   Fujiwara, H ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Circuit faults; Circuit testing; Clocks; Delay; Design for testability; Integrated circuit testing; Multiplexing; Sequential analysis; System testing; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; DESIGN FOR TESTABILITY; ELECTRIC NETWORK ANALYSIS; INTEGER PROGRAMMING; INTEGRATED CIRCUIT DESIGN; MULTIPLEXING; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; TRANSPARENCY; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; DELAY; SEQUENTIAL ANALYSIS; SYSTEM ON A CHIP; SYSTEM TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0142206043     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197665     Document Type: Conference Paper

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