Formal verification of a complex pipelined processor

Formal Methods in System Design

Volumn 23, Issue 2, 2003, Pages 171-213

  Hosabettu, Ravi ^a   Gopalakrishnan, Ganesh ^b   Srivas, Mandayam ^c  

^a SUN MICROSYSTEMS   (United States)

^b UNIVERSITY OF UTAH   (United States)

^c RealChip Communications   (United States)

Author keywords

Completion functions; Formal verification; Processor verification; PVS

Indexed keywords

BUFFER STORAGE; FORMAL LOGIC; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS;

COMPLETION FUNCTIONS; FORMAL VERIFICATION; PROCESSOR VERIFICATION;

PIPELINE PROCESSING SYSTEMS;

EID: 0041822118     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1024716316140     Document Type: Article

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