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Volumn 2102, Issue , 2001, Pages 396-410

Microarchitecture verification by compositional model checking

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; COMPUTER ARCHITECTURE;

EID: 84958763689     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44585-4_40     Document Type: Conference Paper
Times cited : (72)

References (9)
  • 1
    • 0032713623 scopus 로고    scopus 로고
    • Verifying Tomasulo’s algorithm by refinement
    • IEEE Comput. Soc., June
    • T. Arons and A. Pnueli. Verifying Tomasulo’s algorithm by refinement. In 12th Int. Conf. on VLSI Design (VLSI'99), pages 306-9. IEEE Comput. Soc., June 1999.
    • (1999) 12Th Int. Conf. On VLSI Design (VLSI'99) , pp. 306-309
    • Arons, T.1    Pnueli, A.2
  • 2
    • 84958772916 scopus 로고
    • Computer-Aided Verification (CAV94)
    • J. R. Burch and D. L. Dill. Automated verification of pipelined microprocessor control. InD. L. Dill, editor, LNCS 818
    • J. R. Burch and D. L. Dill. Automated verification of pipelined microprocessor control. InD. L. Dill, editor, Computer-Aided Verification (CAV94), LNCS 818, pages 68-80. Springer-Verlag, 1994.
    • (1994) Springer-Verlag , pp. 68-80
  • 3
    • 84944407953 scopus 로고    scopus 로고
    • Verifying advanced microarchitectures that support speculation and exceptions
    • E. A. Emerson and A. P. Sistla, editors, ILNCS 1855, Springer-Verlag
    • R. Hosabettu, G. Gopalakrishnan, and M. Srivas. Verifying advanced microarchitectures that support speculation and exceptions. In E. A. Emerson and A. P. Sistla, editors, Computer-Aided Verification (CAV2000),ILNCS 1855, pages 521-37. Springer-Verlag, 2000.
    • (2000) Computer-Aided Verification (CAV2000) , pp. 521-537
    • Hosabettu, R.1    Gopalakrishnan, G.2    Srivas, M.3
  • 4
    • 0029723683 scopus 로고    scopus 로고
    • ACL2: An industrial strength version of Nqthm
    • IEEE Comp. Soc. Press
    • M. Kaufmann and J. S. Moore. ACL2: An industrial strength version of Nqthm. In Conf. on Computer Assurance (COMPASS-96), pages 23-34. IEEE Comp. Soc. Press, 1996.
    • (1996) Conf. On Computer Assurance (COMPASS-96) , pp. 23-34
    • Kaufmann, M.J.S.M.1
  • 5
    • 0033731380 scopus 로고    scopus 로고
    • A methodology for hardware verification using compositional model checking. Sci. Of Comp
    • K. L. McMillan. A methodology for hardware verification using compositional model checking. Sci. of Comp. Prog., 37(1-3):279-309, May 2000.
    • (2000) Prog , vol.37 , Issue.1 , pp. 279-309
    • McMillan, K.L.1
  • 6
    • 0029251055 scopus 로고
    • Formal verification for fault tolerant architectures: Prolegomena to the design of PVS
    • Feb
    • S. Owre, J. Rushby, N. Shankar, and F. von Henke. Formal verification for fault tolerant architectures: Prolegomena to the design of PVS. IEEE Trans. on Software Eng., 21(2):17-125, Feb 1995.
    • (1995) IEEE Trans. On Software Eng , vol.21 , Issue.2 , pp. 17-125
    • Owre, S.1    Rushby, J.2    Shankar, N.3    Von Henke, F.4
  • 7
    • 84863974979 scopus 로고    scopus 로고
    • Processor verification with precise exceptions and speculative execution
    • A. J. Hu and M. Y. Vardi, editors, LNCS 1427, Springer
    • J. Sawada and W. D. Hunt. Processor verification with precise exceptions and speculative execution. In A. J. Hu and M. Y. Vardi, editors, Computer-Aided Verification (CAV98), LNCS 1427, pages 135-146. Springer, 1998.
    • (1998) Computer-Aided Verification (CAV98) , pp. 135-146
    • Sawada, J.1    Hunt, W.D.2
  • 8
    • 0003081830 scopus 로고
    • An efficient algorithm for exploiting multiple arithmetic units
    • Jan
    • R. M. Tomasulo. An efficient algorithm for exploiting multiple arithmetic units. IBM J. of Research and Development, 11(1):25-33, Jan. 1967.
    • (1967) IBM J. Of Research and Development , vol.11 , Issue.1 , pp. 25-33
    • Tomasulo, R.M.1
  • 9
    • 0033684177 scopus 로고    scopus 로고
    • Formal verification of superscalar micropro­cessors with multicycle functional units, exceptions and branch prediction
    • June
    • M. Velev and R. E. Bryant. Formal verification of superscalar micropro­cessors with multicycle functional units, exceptions and branch prediction. In 37th Design Automation Conference (DAC 2000). IEEE, June 2000.
    • (2000) 37Th Design Automation Conference (DAC 2000). IEEE
    • Velev, M.1    Bryant, R.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.