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Volumn 1785 LNCS, Issue , 2000, Pages 487-502

A comparison of two verification methods for speculative instruction execution

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SCIENCE; COMPUTERS;

EID: 84863896131     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46419-0_33     Document Type: Conference Paper
Times cited : (19)

References (13)
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    • Abadi, M.1    Lamport, L.2
  • 3
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    • Combining symbolic model checking with uninterpreted functions for out-of-order processor verification
    • Formal Methods in Computer-Aided Design
    • S. Berezin, A. Biere, E. Clarke and Y. Zhu. Combining symbolic model checking with uninterpretedfunctions for out-or-order processor verification. FMCAD'98:369-386, Palo Alto, 1998. (Pubitemid 128161791)
    • (1998) Lecture Notes in Computer Science , Issue.1522 , pp. 369-386
    • Berezin, S.1    Biere, A.2    Clarke, E.3    Zhu, Y.4
  • 4
    • 0000938587 scopus 로고    scopus 로고
    • Verifying out-of-order executions
    • Montreal Chapmann & Hall
    • W. Damm and A. Pnueli. Verifying out-of-order executions. CHARME'97:23-47, Montreal, 1997. Chapmann & Hall.
    • (1997) CHARME'97 , pp. 23-47
    • Damm, W.1    Pnueli, A.2
  • 5
    • 0002284699 scopus 로고
    • Intel's p6 uses decoupled superscalar design
    • Gwennap L. Intel's p6 uses decoupled superscalar design. Microprocessor Report, 9(2):9-15, 1995.
    • (1995) Microprocessor Report , vol.9 , Issue.2 , pp. 9-15
    • Gwennap, L.1
  • 7
    • 84863957301 scopus 로고    scopus 로고
    • A proof of correctness of a processor implementing tomasulo's algorithm without a reorder buffer
    • R. Hosabett, G. Gopalakrishnan and M. Srivas. A proof of correctness of a processor implementing Tomasulo's algorithm without a reorder buffer. CHARME' 99.
    • CHARME' 99
    • Hosabett, R.1    Gopalakrishnan, G.2    Srivas, M.3
  • 8
    • 84863924303 scopus 로고    scopus 로고
    • Verification of an implementation of tomasulo's algorithm by compositional model checking
    • Computer Aided Verification
    • K.L. McMillan. Verification of an implementation of Tomasulo's algorithm by compositional model checking. CAV'98:110-121, 1998. (Pubitemid 128092332)
    • (1998) Lecture Notes in Computer Science , Issue.1427 , pp. 110-121
    • McMillan, K.L.1
  • 10
    • 84948983108 scopus 로고    scopus 로고
    • Verification of data-insensitive circuits: An in-order-retirement case study
    • Formal Methods in Computer-Aided Design
    • A. Pnueli, T. Arons. Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study. FMCAD'98:351-368, Palo Alto, 1998. (Pubitemid 128161790)
    • (1998) Lecture Notes in Computer Science , Issue.1522 , pp. 351-368
    • Pnueli, A.1    Arons, T.2
  • 11
    • 84863974979 scopus 로고    scopus 로고
    • Processor verification with precise exceptions and speculative execution
    • Computer Aided Verification
    • J. Sawada and W.A. Hunt Jr.. Processor verification with precise exceptions and speculative execution flushing. CAV'98:135-146, Vancouver, 1998. (Pubitemid 128092334)
    • (1998) Lecture Notes in Computer Science , Issue.1427 , pp. 135-146
    • Sawada, J.1    Hunt, W.A.2
  • 12
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    • Formal verification of out-of-order execution using incremental flushing
    • Vancouver
    • J.U. Skakkebaek, R.B. Jones, and D.L. Dill. Formal verification of out-of-order execution using incremental flushing. CAV'98:pp 98-110, Vancouver, 1998.
    • (1998) CAV'98 , pp. 98-110
    • Skakkebaek, J.U.1    Jones, R.B.2    Dill, D.L.3
  • 13
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    • An efficient algorithm for exploiting multiple arithmetic units
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    • Tomasulo, R.M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.