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Volumn 1522, Issue , 1998, Pages 369-386
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Combining symbolic model checking with uninterpreted functions forout-of-order processor verification
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER AIDED DESIGN;
COMPUTER ARCHITECTURE;
FORMAL METHODS;
DECISION PROCEDURE;
INSTRUCTION SCHEDULING;
INSTRUCTION SET ARCHITECTURE;
REDUCTION TECHNIQUES;
SYMBOLIC MODEL CHECKERS;
SYMBOLIC MODEL CHECKING;
UNINTERPRETED FUNCTION SYMBOLS;
UNINTERPRETED FUNCTIONS;
MODEL CHECKING;
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EID: 35248886365
PISSN: 03029743
EISSN: 16113349
Source Type: Book Series
DOI: 10.1007/3-540-49519-3_24 Document Type: Conference Paper |
Times cited : (27)
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References (24)
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