메뉴 건너뛰기




Volumn 1522, Issue , 1998, Pages 351-368

Verification of data-insensitive circuits: An in-order-retirement case study

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FORMAL METHODS; TIMING CIRCUITS;

EID: 84948983108     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-49519-3_23     Document Type: Conference Paper
Times cited : (10)

References (34)
  • 6
    • 84958772916 scopus 로고
    • Automatic verification of pipelined microprocessor control
    • J. R. Burch and D. L. Dill. Automatic verification of pipelined microprocessor control. CAV'94:68-80, 1994.
    • (1994) CAV'94 , pp. 68-80
    • Burch, J.R.1    Dill, D.L.2
  • 7
    • 84949055854 scopus 로고    scopus 로고
    • Model-checking in a microprocessor design project
    • G. Barrett and A. McIsaac. Model-checking in a microprocessor design project. CAV'97, 1997.
    • (1997) CAV'97
    • Barrett, G.1    McIsaac, A.2
  • 9
    • 0003011657 scopus 로고    scopus 로고
    • Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fixpoints
    • P. Cousot and R. Cousot. Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fixpoints. POPL'77.
    • POPL'77
    • Cousot, P.1    Cousot, R.2
  • 11
    • 84947707419 scopus 로고
    • Verifying parametrized networks using abstraction and regular languages
    • E.M. Clarke, O. Grumberg, and S. Jha. Verifying parametrized networks using abstraction and regular languages. CONCUR'95:395-407, 1995.
    • (1995) CONCUR'95 , pp. 395-407
    • Clarke, E.M.1    Grumberg, O.2    Jha, S.3
  • 14
    • 84957704040 scopus 로고
    • Ground temporal logic: A logic for hardware verification
    • D. Cyrluk and P. Narendran. Ground temporal logic: A logic for hardware verification. CAV'94:247-259, 1994.
    • (1994) CAV'94 , pp. 247-259
    • Cyrluk, D.1    Narendran, P.2
  • 17
    • 84949055858 scopus 로고    scopus 로고
    • Herbrand automata for hardware verification
    • W. Damm, A. Pnueli, and S. Ruah. Herbrand automata for hardware verification. CONCUR'98, 1998.
    • (1998) CONCUR'98
    • Damm, W.1    Pnueli, A.2    Ruah, S.3
  • 20
    • 0026945671 scopus 로고
    • An experience in proving regular networks of processes by modular model checking
    • N. Halbwachs, F. Lagnier, and C. Ratel. An experience in proving regular networks of processes by modular model checking. Acta Informatica, 29(6/7):523-543, 1992.
    • (1992) Acta Informatica , vol.29 , Issue.6-7 , pp. 523-543
    • Halbwachs, N.1    Lagnier, F.2    Ratel, C.3
  • 22
    • 84948966713 scopus 로고    scopus 로고
    • The need for formal methods for integrated circuit design
    • K. Keutzer. The need for formal methods for integrated circuit design. FMCAD'96:1-18, 1996.
    • (1996) FMCAD'96 , pp. 1-18
    • Keutzer, K.1
  • 25
    • 0002284699 scopus 로고
    • Intel's p6 uses decoupled superscalar design
    • Gwennap L. Intel's p6 uses decoupled superscalar design. Microprocessor Report, 9(2):9-15, 1995.
    • (1995) Microprocessor Report , vol.9 , Issue.2 , pp. 9-15
    • Gwennap, L.1
  • 27
    • 84949055861 scopus 로고    scopus 로고
    • A compositional rule for hardware design refinement
    • K.L. McMillan. A compositional rule for hardware design refinement. CAV'97.
    • CAV'97
    • McMillan, K.L.1
  • 28
    • 84863924303 scopus 로고    scopus 로고
    • Verification of an implementation of Tomasulo's algorithm by compositional model checking
    • K.L. McMillan. Verification of an implementation of Tomasulo's algorithm by compositional model checking. CAV'98:110-121, 1998.
    • (1998) CAV'98 , pp. 110-121
    • McMillan, K.L.1
  • 32
    • 84863960247 scopus 로고    scopus 로고
    • Formal verification of out-of-order execution using incremental flushing
    • J.U. Skakkebaek, R.B. Jones, and D.L. Dill. Formal verification of out-of-order execution using incremental flushing. CAV'98:pp 98-110, 1998.
    • (1998) CAV'98 , pp. 98-110
    • Skakkebaek, J.U.1    Jones, R.B.2    Dill, D.L.3
  • 33
    • 84863974979 scopus 로고    scopus 로고
    • Processor verification with precise exceptions and speculative execution flushing
    • J. Sawada and W.A. Hunt Jr. Processor verification with precise exceptions and speculative execution flushing. CAV'98:135-146, 1998.
    • (1998) CAV'98 , pp. 135-146
    • Sawada, J.1    Hunt, W.A.2
  • 34
    • 0003081830 scopus 로고
    • An efficient algorithm for exploiting multiple arithmetic units
    • R.M. Tomasulo. An efficient algorithm for exploiting multiple arithmetic units. IBM J. of Research and Development, 11(1):25-33, 1967.
    • (1967) IBM J. Of Research and Development , vol.11 , Issue.1 , pp. 25-33
    • Tomasulo, R.M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.