-
1
-
-
0003149666
-
Wire delay in the presence of crosstalk
-
G. Yee, R. Chandra, V. Ganesan, and C. Sechen, "Wire delay in the presence of crosstalk," in Proc. TAU, 1997, pp. 170-175.
-
(1997)
Proc. TAU
, pp. 170-175
-
-
Yee, G.1
Chandra, R.2
Ganesan, V.3
Sechen, C.4
-
3
-
-
0024933412
-
Dynamic noise margins of MOS logic gates
-
J. M. Zurada, Y. S. Joo, and S. V. Bell, "Dynamic noise margins of MOS logic gates," Proc. IEEE ISCAS, pp. 1153-1156, 1989.
-
(1989)
Proc. IEEE ISCAS
, pp. 1153-1156
-
-
Zurada, J.M.1
Joo, Y.S.2
Bell, S.V.3
-
4
-
-
0031338892
-
Global harmony: Coupled noise analysis for full-chip RC interconnect networks
-
K. L. Shepard, V. Narayanan, P. C. Elemendorf, and G. Zheng, "Global harmony: Coupled noise analysis for full-chip RC interconnect networks," in Proc. Int. Conf. Comput.-Aided Design, 1997, pp. 139-146.
-
(1997)
Proc. Int. Conf. Comput.-Aided Design
, pp. 139-146
-
-
Shepard, K.L.1
Narayanan, V.2
Elemendorf, P.C.3
Zheng, G.4
-
5
-
-
0031619509
-
Design methodologies for noise in digital integrated circuits
-
K. L. Shepard, "Design methodologies for noise in digital integrated circuits," Proc. ACM/IEEE Design Automation Conf., pp. 94-99, 1998.
-
(1998)
Proc. ACM/IEEE Design Automation Conf.
, pp. 94-99
-
-
Shepard, K.L.1
-
6
-
-
0033685443
-
Clarinet: A noise analysis tool for deep submicron design
-
June
-
R. Levy, D. Blaauw, G. Braca, A. Dasgupta, A. Grinshpon, C. Oh, B. Orshav, S. Sirichotiyakul, and V. Zolotov, "Clarinet: A noise analysis tool for deep submicron design," Proc. IEEE/ACM Design Automat. Conf., pp. 233-238, June 2000.
-
(2000)
Proc. IEEE/ACM Design Automat. Conf.
, pp. 233-238
-
-
Levy, R.1
Blaauw, D.2
Braca, G.3
Dasgupta, A.4
Grinshpon, A.5
Oh, C.6
Orshav, B.7
Sirichotiyakul, S.8
Zolotov, V.9
-
7
-
-
0012837457
-
An analytical model for delay and crosstalk estimation with application to decoupling
-
M. Becer and I. J. Hajj, "An analytical model for delay and crosstalk estimation with application to decoupling," Proc. IEEE Int. Symp. Quality Electron. Design, pp. 51-57, 2000.
-
(2000)
Proc. IEEE Int. Symp. Quality Electron. Design
, pp. 51-57
-
-
Becer, M.1
Hajj, I.J.2
-
8
-
-
85030259511
-
Noise and delay uncertainty studies for coupled RC interconnects
-
A. B. Kahng, S. Muddu, and D. Vidhani, "Noise and delay uncertainty studies for coupled RC interconnects," in Proc. ASIC/SOC Conf., 1999, pp. 3-8.
-
(1999)
Proc. ASIC/SOC Conf.
, pp. 3-8
-
-
Kahng, A.B.1
Muddu, S.2
Vidhani, D.3
-
9
-
-
0010832489
-
Post global routing crosstalk risk estimation and reduction
-
T. Xue, E. S. Kuh, and D. Wang, "Post global routing crosstalk risk estimation and reduction," Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 616-619, 1994.
-
(1994)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Design
, pp. 616-619
-
-
Xue, T.1
Kuh, E.S.2
Wang, D.3
-
10
-
-
0027222295
-
Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's
-
Jan.
-
T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, pp. 118-124, Jan. 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, pp. 118-124
-
-
Sakurai, T.1
-
11
-
-
0033320052
-
Crosstalk in VLSI interconnections
-
Dec.
-
A. Vittal, L. H. Chen, M. Marek-Sadowska, K.-P. Wang, and S. Yang, "Crosstalk in VLSI interconnections," IEEE Trans. Comput.-Aided Design Integral. Circuits Syst., vol. 18, no. 12, pp. 1817-1824, Dec. 1999.
-
(1999)
IEEE Trans. Comput.-Aided Design Integral. Circuits Syst.
, vol.18
, Issue.12
, pp. 1817-1824
-
-
Vittal, A.1
Chen, L.H.2
Marek-Sadowska, M.3
Wang, K.-P.4
Yang, S.5
-
12
-
-
0031336414
-
Efficient coupled noise estimation for on-chip interconnects
-
A. Devgan, "Efficient coupled noise estimation for on-chip interconnects," Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 147-153, 1997.
-
(1997)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Design
, pp. 147-153
-
-
Devgan, A.1
-
13
-
-
0033297670
-
Efficient crosstalk estimation
-
M. Kuhlmann, S. S. Sapatnekar, and K. K. Parhi, "Efficient crosstalk estimation," in Proc. Int. Conf. Comput. Design, 1999, pp. 266-272.
-
(1999)
Proc. Int. Conf. Comput. Design
, pp. 266-272
-
-
Kuhlmann, M.1
Sapatnekar, S.S.2
Parhi, K.K.3
-
14
-
-
0031619501
-
Buffer insertion for noise and delay optimization
-
C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer insertion for noise and delay optimization," in Proc. Design Automat. Conf., 1998, pp. 362-367.
-
(1998)
Proc. Design Automat. Conf.
, pp. 362-367
-
-
Alpert, C.J.1
Devgan, A.2
Quay, S.T.3
-
15
-
-
0010359828
-
A global driver sizing tool for functional crosstalk noise avoidance
-
M. R. Becer, D. Blaauw, S. Sirichotiyakul, R. Levy, C. Oh, V. Zolotov, J. Zuo, and I. J. Hajj, "A global driver sizing tool for functional crosstalk noise avoidance," Proceedings IEEE Int. Symp. Quality Electron. Design, pp. 158-163, 2001.
-
(2001)
Proceedings IEEE Int. Symp. Quality Electron. Design
, pp. 158-163
-
-
Becer, M.R.1
Blaauw, D.2
Sirichotiyakul, S.3
Levy, R.4
Oh, C.5
Zolotov, V.6
Zuo, J.7
Hajj, I.J.8
-
16
-
-
0031683754
-
Analysis, reduction and avoidance of crosstalk on VLSI chips
-
T. STohr, H. Alt, A. Hetzel, and K. Koehl, "Analysis, reduction and avoidance of crosstalk on VLSI chips," in Proc. Int. Symp. Physical Design, 1998, pp. 211-218.
-
(1998)
Proc. Int. Symp. Physical Design
, pp. 211-218
-
-
Stohr, T.1
Alt, H.2
Hetzel, A.3
Koehl, K.4
-
20
-
-
0033698637
-
On switching factor based analysis of coupled RC interconnects
-
A. B. Kahng, S. Muddu, and E. Sarto, "On switching factor based analysis of coupled RC interconnects," Proc. IEEE/ACM Design Automat. Conf., pp. 79-84, 2000.
-
(2000)
Proc. IEEE/ACM Design Automat. Conf.
, pp. 79-84
-
-
Kahng, A.B.1
Muddu, S.2
Sarto, E.3
-
21
-
-
0031378497
-
PRIMA: Passive reduced-order interconnect macromodeling algorithm
-
A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," in Proc. Int. Conf. Comput.-Aided Design, 1997, pp. 58-65.
-
(1997)
Proc. Int. Conf. Comput.-Aided Design
, pp. 58-65
-
-
Odabasioglu, A.1
Celik, M.2
Pileggi, L.T.3
-
22
-
-
0043196449
-
Signal integrity in high performance design
-
D. Blaauw, A. Dharchoudhurry, and A. Devgan, "Signal integrity in high performance design," in Tutorial Presentation, IEEE/ACM Int. Conf. Comput.-Aided Design, 1999.
-
(1999)
Tutorial Presentation, IEEE/ACM Int. Conf. Comput.-Aided Design
-
-
Blaauw, D.1
Dharchoudhurry, A.2
Devgan, A.3
-
23
-
-
0030141612
-
Performance computation for precharacterized CMOS gates with RC loads
-
May
-
F. Dartu, N. Menezes, and L. T. Pileggi, "Performance computation for precharacterized CMOS gates with RC loads," IEEE Trans. Comput.-Aided Design of Integrat. Circuits Syst., vol. 15, no. 5, pp. 544-553, May 1996.
-
(1996)
IEEE Trans. Comput.-Aided Design of Integrat. Circuits Syst.
, vol.15
, Issue.5
, pp. 544-553
-
-
Dartu, F.1
Menezes, N.2
Pileggi, L.T.3
-
24
-
-
0028756124
-
Modeling the effective capacitance for the RC interconnect of CMOS gates
-
Dec.
-
J. Qian, S. Pullela, and L. T. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. Comput.-Aided Design, pp. 1526-1555, Dec. 1994.
-
(1994)
IEEE Trans. Comput.-Aided Design
, pp. 1526-1555
-
-
Qian, J.1
Pullela, S.2
Pillage, L.T.3
-
25
-
-
0030686019
-
Calculating worst-case gate delays due to dominant capacitance coupling
-
June
-
F. Dartu and L. T. Pileggi, "Calculating worst-case gate delays due to dominant capacitance coupling," in Proc. DAC, June 1997, pp. 46-51.
-
(1997)
Proc. DAC
, pp. 46-51
-
-
Dartu, F.1
Pileggi, L.T.2
-
26
-
-
0032319737
-
Determination of worst-case aggressor alignment for delay calculation
-
Nov.
-
P. D. Gross, R. Arunachalam, K. Rajagopal, and L. T. Pileggi, "Determination of worst-case aggressor alignment for delay calculation," Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 212-219, Nov. 1998.
-
(1998)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Design
, pp. 212-219
-
-
Gross, P.D.1
Arunachalam, R.2
Rajagopal, K.3
Pileggi, L.T.4
-
27
-
-
0033885244
-
Capturing the effect of crosstalk on delay
-
Jan.
-
S. Sapatnekar, "Capturing the effect of crosstalk on delay," in Proc. VLSI Design 2000, Jan. 2000, pp. 364-369.
-
(2000)
Proc. VLSI Design 2000
, pp. 364-369
-
-
Sapatnekar, S.1
-
28
-
-
0033698156
-
TACO: Timing anal-ysis with coupling
-
June
-
R. Arunachalam, K. Rajagopal, and L. T. Pileggi, "TACO: Timing anal-ysis with coupling," in Proc. Design Automat. Conf., June 2000, pp. 266-269.
-
(2000)
Proc. Design Automat. Conf.
, pp. 266-269
-
-
Arunachalam, R.1
Rajagopal, K.2
Pileggi, L.T.3
-
29
-
-
84949777577
-
Switching window computation for static timing analysis in the presence of crosstalk noise
-
P. Chen, D. A. Kirkpatrick, and K. Keutzer, "Switching window computation for static timing analysis in the presence of crosstalk noise," Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 331-337, 2000.
-
(2000)
Proc. IEEE/ACM Int. Conf. Comput.-Aided Design
, pp. 331-337
-
-
Chen, P.1
Kirkpatrick, D.A.2
Keutzer, K.3
-
30
-
-
85013972107
-
Crosstalk delay analysis using relative window method
-
Y. Sasaki and G. De Micheli, "Crosstalk delay analysis using relative window method," in IEEE Int. ASIC/SOC Conf., 1999, pp. 9-13.
-
(1999)
IEEE Int. ASIC/SOC Conf.
, pp. 9-13
-
-
Sasaki, Y.1
De Micheli, G.2
-
32
-
-
0035333780
-
Aggressor alignment for worst-case crosstalk noise
-
May
-
L. H. Chen and M. Marek-Sadowska, "Aggressor alignment for worst-case crosstalk noise," IEEE Trans. Comput.-Aided Design, vol. 20, pp. 612-621, May 2001.
-
(2001)
IEEE Trans. Comput.-Aided Design
, vol.20
, pp. 612-621
-
-
Chen, L.H.1
Marek-Sadowska, M.2
|