Determination of worst-case aggressor alignment for delay calculation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages 212-219

  Gross, Paul D ^a   Arunachalam, Ravishankar ^a   Rajagopal, Karthik ^a   Pileggi, Lawrence T ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTATIONAL COMPLEXITY; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; ITERATIVE METHODS; LOGIC GATES; WAVEFORM ANALYSIS;

DEEP SUBMICRON TECHNOLOGIES; DELAY CALCULATIONS; WORST-CASE AGGRESSOR ALIGNMENTS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032319737     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/288548.288616     Document Type: Conference Paper

References (18)