ClariNet: A noise analysis tool for deep submicron design

Proceedings-Design Automation Conference

Volumn , Issue , 2000, Pages 233-238

  Levy, Rafi ^a,b   Blaauw, David ^a,b   Braca, Gabi ^a   Dasgupta, Aurobindo ^a,b   Grinshpon, Amir ^a   Oh, Chanhee ^a   Orshav, Boaz ^a   Sirichotiyakul, Supamas ^a   Zolotov, Vladimir ^a  

^a MOTOROLA INC   (United States)

^b Motorola Israel Ltd   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; COMPUTER AIDED SOFTWARE ENGINEERING; DIGITAL SIGNAL PROCESSING; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; LOGIC CIRCUITS; LOGIC GATES; MICROPROCESSOR CHIPS; SIGNAL FILTERING AND PREDICTION;

NOISE ANALYSIS TOOL; SOFTWARE PACKAGE CLARINET;

SPURIOUS SIGNAL NOISE;

EID: 0033685443     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2000.855309     Document Type: Article

References (8)

1. A. Devgan Efficient coupled noise estimation for on-chip interconnects Proc. IEEE Intl. Conf. Computer-Aided Design 147 151 Proc. IEEE Intl. Conf. Computer-Aided Design 1997-Nov.
2. A. Dharchoudhury D. Blaauw J. Norton S. Pullela J. Dunning Transistor-level sizing and timing verification of domino circuits in the PowerPCTM microprocessor Proc. Intl. Conf. Computer Design 143 148 Proc. Intl. Conf. Computer Design 1997
3. M. Kuhlmann S. S. Sapatnekar K. K. Parhi Efficient crosstalk Estimation Proc. IEEE Intl. Conf. Computer Design 266 272 Proc. IEEE Intl. Conf. Computer Design 1999-Oct
4. A. Odabasioglu M. Celik L. T. Pileggi PRIMA: Passive reduced-order interconnect macromodeling algorithm Proc. Intl. Conf. Computer-Aided Design 58 65 Proc. Intl. Conf. Computer-Aided Design 1997
5. J. Qian S. Pullela L. T. Pillage Modeling the effective capacitance for the RC interconnect of CMOS gates IEEE Trans. Computer-Aided Design 1526 1555 Dec 1994
6. K. L. Sheppard V. Narayanan P. C. Elementary G. Zheng Global Harmony: Coupled noise analysis for full-chip RC interconnect networks Proc. Intl. Conf. Computer-Aided Design 139 146 Proc. Intl. Conf. Computer-Aided Design 1997
7. J. M. Zurada Y. S. Joo S. V. Bell Dynamic noise margins of MOS logic gates Proc. IEEE ISCAS 1153 1156 Proc. IEEE ISCAS 1989
8. V. Zolotov Closed form noise filter expressions Motorola