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Volumn 93, Issue 6, 2003, Pages 3545-3552

Effect of Si cap layer on parasitic channel operation in Si/SiGe metal-oxide-semiconductor structures

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; ETCHING; INTERFACES (MATERIALS); MOSFET DEVICES; OXIDATION; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE STRUCTURES; THERMAL EFFECTS;

EID: 0037444970     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1542916     Document Type: Article
Times cited : (17)

References (34)
  • 24
    • 0012962464 scopus 로고
    • Ph.D. dissertation, University of California, Los Angeles
    • D. K. Nayak, Ph.D. dissertation, University of California, Los Angeles, 1992.
    • (1992)
    • Nayak, D.K.1
  • 27
    • 0012961236 scopus 로고    scopus 로고
    • Fabrication of high quality MOS structures with SiGe buried channels for CMOS applications
    • Washington D.C.
    • S. Kar and P. Zaumseil, Fabrication of High Quality MOS Structures with SiGe Buried Channels for CMOS Applications, 199th Electrochemical Meeting, Washington D.C., 2001, p. 409.
    • (2001) 199th Electrochemical Meeting , pp. 409
    • Kar, S.1    Zaumseil, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.