Improved method for the oxide thickness extraction in MOS structures with ultrathin gate dielectrics

IEEE Transactions on Semiconductor Manufacturing

Volumn 13, Issue 2, 2000, Pages 152-158

  Ghibaudo, Gérard ^a,b   Bruyère, Sylvie ^b,c   Devoivre, Thierry ^b,c   DeSalvo, Barbara ^b   Vincent, Emmanuel ^c  

^a IEEE   (France)

^b CNRS   (France)

^c STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

MASERJIANS TECHNIQUE; MOS STRUCTURES; OXIDE THICKNESS EXTRACTION; ULTRATHIN GATE DIELECTRICS; VINCENTS METHOD;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; OXIDES; SEMICONDUCTOR DEVICE STRUCTURES;

MOS CAPACITORS;

EID: 0033688062     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.843630     Document Type: Article

References (4)

1. S. Walstra and C. T. Sah, "Thin oxide thickness extrapolation from capacitance voltage measurements," IEEE Trans. Electron Devices, vol. 44, pp. 1136-1142, 1997.
2. E. Vincent, G. Ghibaudo, G. Morin, and C. Papadas, "On the oxide thickness extraction in deep submicron technologies," in Proc. IEEE 1997 Int. Conf. Microelectron. Test Structures, vol. 10, Mar. 1997, pp. 105-110.
3. J. Maserjian, G. Petersen, and C. Svensson, "Saturation capacitance of thin oxide MOS structures and the effective surface density of states of silicon," Solid State Electron., vol. 17, pp. 335-339, 1974
4. B. Ricco, R. Versari, and D. Esseni, "Characterization of polysilicon gate depletion in MOS structure," IEEE Trans. Electron Devices, vol. 17, pp. 103-105, 1996.