Chip-level charged-device modeling and simulation in CMOS integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 1, 2003, Pages 67-81

  Lee, Jaesik ^a,b   Kim, Ki Wook ^c   Huh, Yoonjong ^d   Bendix, Peter ^d   Kang, Sung Mo ^e  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b LUCENT TECHNOLOGIES   (United States)

^c SiPackets Inc   (United States)

^d AGERE SYSTEMS   (United States)

^e University of California   (United States)

Author keywords

Extraction; Modeling; Reliability; Simulation

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHARGE TRANSFER; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC DISCHARGES; ELECTROSTATICS; RELIABILITY; SCANNING ELECTRON MICROSCOPY;

CHARGED-DEVICE MODELS (CDM); ELECTROSTATIC DISCHARGES (ESD);

CMOS INTEGRATED CIRCUITS;

EID: 0037233326     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.805720     Document Type: Article

References (28)

1. S. Halperin, "Guidelines for static control management," in Proc. Eurostat, 1990, pp. 452-461.
2. Electrostatic Discharge Control Handbook, Lucent Technologies, Murray Hill, NJ, 1997.
3. Y. Fukuda, S. Ishiguro, and M. Takahara, "ESD protection network evaluation by HBM and CPM," in Proc. Int. Symp. EOS/ESD, 1986, pp. 193-199.
4. J. Stathis and D. DiMaria, "Reliability projection for ultra-thin oxides at low voltage," in Proc. Int. Electron Devices Meeting, 1998, pp. 167-170.
5. C. Leroux et al., "Analysis of oxide breakdown mechanism occurring during ESD pulse," in Proc. IEEE Int. Reliability Physics Symp., 2000, pp. 276-282.
6. S. Ramaswamy, E. Li, E. Rosenbaum, and S. M. Kang, "Circuit-level simulation of CDM-ESD and EOS in submicron MOS device," in Proc. Int. Symp. EOS/ESD, 1996, pp. 316-321.
7. C. Duvvury and A. Amerasekera, "Advanced CMOS protection device trigger mechanisms during CDM," in Proc. Int. Symp. EOS/ESD, 1995, pp. 162-174.
8. S. Beebe, "Simulation of complete CMOS I/O circuit response to CDM stress," in Proc. Int. Symp. EOS/ESD, 1998, pp. 259-270.
9. K. Verhaege, C. Russ, J. Luchies, G. Groeseneken, and F. Kuper, "Grounded-gate nMOS transistor behavior under CDM ESD stress conditions," IEEE Trans. Electron Devices, vol. 44, pp. 1972-1980, Nov. 1997.
10. A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm," IEEE Trans. Computer-Aided Design, vol. 17, pp. 645-654, Aug. 1997.
11. T. Li and S. M. Kang, "Layout extraction and verification methodology for CMOS I/O circuits," in Proc. ACM/IEEE Design Automation Conf., 1998, pp. 291-296.
12. W. Greason, "Analysis of the charge transfer of models for electrostatic discharge (ESD) and semiconductor devices," IEEE Trans. Ind. Applicat., vol. 32, pp. 726-734, May/June 1996.
13. J. Vinson and J. Liou, "Electrostatic discharge in semiconductor devices: An overview," Proc. IEEE, vol. 86, pp. 399-418, Feb. 1998.
14. S. Dabral and T. Maloney, Basic ESD and I/O Design. New York: Wiley, 1998.
15. K. Verhaege, V. Groeseneken, H. Maes, P. Egger, and H. Gieser, "Influence of tester, test method and device type on CDM ESD testing," IEEE Trans. Comp., Packag., Manufact. Technol., vol. 18, pp. 284-293, June 1995.
16. J. Lee, Y. Huh, J. Chen, P. Bendix, and S. Kang, "Chip-level simulation for CDM failures in multi-power IC's," in Proc. Int. Symp. EOS/ESD, 2000, pp. 456-464.
17. T. Wada, "ESD evaluation methods for a charged device model," IEEE Trans. Comp., Packag., Manufact. Technol., vol. 19, pp. 162-168, July 1996.
18. R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits. New York: Wiley, 1986.
19. M. Kerr, C. Wu, H. Chang, and T. Wu, "Whole chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology," in Proc. IEEE Custom Integrated Circuits Conf., 1997, pp. 31-34.
20. T. J. Maloney, "Designing MOS inputs and outputs to avoid oxide failure in the charged device model," in Proc. Int. Symp. EOS/ESD, 1988, pp. 220-227.
21. N. Maene, J. Vandenbroeck, and V. Bempt, "Failure analysis of CDM failure in a mixed analog/digital circuit," in Proc. Int. Symp. EOS/ESD, 1994, pp. 307-314.
22. P. J. H. Elias and N. P. van der Meijs, "Extracting circuit models for large RC interconnections that are accurate up to a predefined signal frequency," in Proc. ACM/IEEE Design Automation Conf., 1996, pp. 764-769.
23. M. Zhao, R. V. Panda, S. S. Sapatnekar, T. Edwards, R. Chaudhary, and D. Blaauw, "Hierarchical analysis of power distribution networks," in Proc. ACM/IEEE Design Automation Conf., 2000, pp. 150-155.
24. A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan, B. Tutuianu, and D. Bearden, "Design and analysis of power distribution networks in powerPC microprocessors," in Proc. ACM/IEEE Design Automation Conf., 1998, pp. 738-743.
25. G. Steele, D. Overhauser, S. Rochel, and Z. Hussain, "Full-chip verification methods for DSM power distribution systems," in Proc. ACM/IEEE Design Automation Conf., 1998, pp. 744-749.
26. M. Tanaka and K. Okada, "CDM ESD test considered phenomena of division and reduction of high voltage discharge in the environment," in Proc. Int. Symp. EOS/ESD, 1996, pp. 54-61.
27. Y. Fong and C. Hu, "The effects of high electric field transients on thin gate oxide MOSFET's,' in Proc. Int. Symp. EOS/ESD, 1987, pp. 252-257.
28. J. Wu, P. Juliano, and E. Rosenbaum, "Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions," in Proc. Int. Symp. EOS/ESD, 2000, pp. 287-295.