Layout extraction and verification methodology for CMOS I/O circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 291-296

  Li, Tong ^a   Kang, Sung Mo ^b  

^a University of Illinois at Urbana Champaign   (United States)

^b United States of America   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC RECTIFIERS; ELECTROSTATIC DEVICES; EXTRACTION; MOS DEVICES; TIMING CIRCUITS; BIPOLAR TRANSISTORS; ELECTRIC DISCHARGES; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

CIRCUIT LEVELS; ELECTRO-STATIC DISCHARGE (ESD); ESD STRESS; LAYOUT EXTRACTION; NEW DEVICES; NOVEL TECHNIQUES; RELIABILITY-DRIVEN; VERIFICATION METHODOLOGY;

INTEGRATED CIRCUIT LAYOUT; CMOS INTEGRATED CIRCUITS;

ELECTROSTATIC DISCHARGE;

EID: 0031642075     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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