Designing the best clock distribution network

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1998, Pages 2-5

  Restle, Phillip J ^a   Deutsch, Alina ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; TRANSMISSION LINE THEORY; VLSI CIRCUITS;

CLOCK DISTRIBUTION NETWORKS;

TIMING CIRCUITS;

EID: 0031640596     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)