Multilevel Metal Capacitance Models for CAD Design Synthesis Systems

IEEE Electron Device Letters

Volumn 13, Issue 1, 1992, Pages 32-34

  Chern, Jue Hsien ^a   Huang, Jean ^b   Arledge, Lawrence ^b   Li, Ping Chung ^b   Yang, Ping ^b  

^a TEXAS INSTRUMENTS   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; ELECTRIC WIRING;

CROSSOVER CAPACITANCE; LINE-TO-LINE CAPACITANCE; MULTILEVEL METAL CAPACITANCE MODELS;

INTEGRATED CIRCUITS;

EID: 0026626371     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.144942     Document Type: Article

References (5)

1. J.H. Chern, J.T. Maeda, L.A. Arledge, and P. Yang, “SIERRA: A 3-D device simulator for reliability modeling,” IEEE Trans. Computer-Aided Design, vol. 8, no. 5, pp. 516–527, 1989.
2. W.H. Chang, “Analytic IC-metal-line capacitance formulas,” IEEE Trans. Microwave Theory and Tech., vol. MTT-24, pp. 608–611, 1976.
3. M.I. Elmasry, “Capacitance calculation in MOSFET VLSI,” IEEE Electron Device Lett., vol. EDL-3, pp. 6–7, 1981.
4. C.P. Yuan and T.N. Trick, “A simple formula for the estimation of the capacitance of two-dimensional interconnects in VLSI circuits,” IEEE Electron Device Lett., vol. EDL-3, no. 12, pp. 391–393, 1982.
5. T. Sakurai and K. Tamaru, “Simple formulas for two- and three-dimensional capacitances,” IEEE Trans. Electron Devices, vol. ED-30, pp. 183–185, 1983.