Interconnect performance estimation models for design planning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 6, 2001, Pages 739-752

  Cong, Jason ^a,b   Pan, Zhigang ^a,c  

^a IEEE   (United States)

^b University of California   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Buffer insertion and sizing; Design planning; Driver sizing; Interconnect estimation; Wire sizing

Indexed keywords

INTERCONNECT LAYOUT OPTIMIZATION TECHNIQUES; INTERCONNECT PERFORMANCE ESTIMATION MODELS; SOFTWARE PACKAGE TREE-REPEATER-INTERCONNECT-OPTIMIZATION;

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; EXTRAPOLATION; INTEGRATED CIRCUIT LAYOUT; INTERPOLATION; OPTIMIZATION; PERFORMANCE; THEOREM PROVING;

SEMICONDUCTOR DEVICE MODELS;

EID: 0035368267     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.924827     Document Type: Article

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