UST/DME: A clock tree router for general skew constraints

ACM Transactions on Design Automation of Electronic Systems

Volumn 7, Issue 3, 2002, Pages 359-379

  Tsao, Chung Wen Albert ^a   Koh, Cheng Kok ^b  

^a Celestry Design Technologies Inc   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Clock tree; Feasible skew range; Incremental skew scheduling; Merging and embedding; Merging region; Useful Skew

Indexed keywords

ALGORITHMS; CLOCKS; CONSTRAINT THEORY; MATHEMATICAL MODELS; OPTIMIZATION; ROUTERS;

CLOCK TREE ROUTERS; SKEW CONSTRAINTS;

DIGITAL SIGNAL PROCESSING;

EID: 0036660080     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/567270.567271     Document Type: Article

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