Efficient retiming of large circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 1, 1998, Pages 74-83

  Maheshwari, Naresh ^a,b   Sapatnekar, Sachin ^a,c  

^a IEEE   (United States)

^b Iowa State University of Science and Technology   (United States)

^c University of Minnesota   (United States)

Author keywords

Circuit optimization; Design automation software; Linear programming; Logic synthesis; Sequential logic circuits; Very large scale integration

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SOFTWARE; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SEQUENTIAL CIRCUITS; TIMING CIRCUITS;

CIRCUIT RETIMING; LOGIC SYNTHESIS; MINARET ALGORITHM;

VLSI CIRCUITS;

EID: 0032028272     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.661250     Document Type: Article

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