Jitter-tolerant clock routing in two-phase synchronous systems

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 316-320

  Xi, Joe G ^a   Dai, Wayne W M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; PHASE SHIFT; SIMULATED ANNEALING; SPURIOUS SIGNAL NOISE; SYNCHRONIZATION;

BOUNDED SKEW TREE (BST); DEFERRED MERGE EMBEDDING (DME) FRAMEWORK; JITTER TOLERANT CLOCK ROUTING; TWO PHASE SYNCHRONOUS SYSTEMS;

TIMING CIRCUITS;

EID: 0030381852     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)