Clock-skew optimization for peak current reduction

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1996, Pages 265-270

  Vuillod, P ^a   Benini, L ^a   Bogliolo, A ^a   De Micheli, G ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC CURRENTS; ELECTRIC POWER SYSTEMS; ENERGY DISSIPATION; ENERGY UTILIZATION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; SIGNAL PROCESSING; VLSI CIRCUITS;

BENCHMARK CIRCUITS; CLOCK SKEW OPTIMIZATION; SEQUENTIAL LOGIC ELEMENTS; SIGNAL PROPAGATION; SYNCHRONOUS DIGITAL CIRCUITS;

DIGITAL CIRCUITS;

EID: 0030382578     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)