Planar-DME: A single-layer zero-skew clock tree router

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 1, 1996, Pages 8-19

  Kahng, Andrew B ^a   Tsao, Chung Wen Albert ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; MATHEMATICAL MODELS; TREES (MATHEMATICS);

CLOCK TREE ROUTING; CONNECTION TOPOLOGY; DEFERRED MERGE EMBEDDING; ELMORE DELAY MODEL; LINEAR DELAY MODEL; ZERO SKEW;

COMPUTER AIDED DESIGN;

EID: 0029771183     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.486268     Document Type: Article

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