Useful-Skew Clock Routing with Gate Sizing for Low Power Design

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 16, Issue 2-3, 1997, Pages 163-179

  Xi, Joe Gufeng ^{a,b,c,d,e,f,g}   Dai, Wayne Wei Ming ^a,h  

^a University of California Santa Cruz   (United States)

^b Ultima Interconnect Technology Inc   (United States)

^c SHANGHAI JIAO TONG UNIVERSITY   (China)

^d SYRACUSE UNIVERSITY   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^g Chips and Technology Inc   (United States)

^h UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL SIGNAL PROCESSING; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; PERTURBATION TECHNIQUES; SIMULATED ANNEALING; TREES (MATHEMATICS);

DEFERRED MERGE EMBEDDING (DME) APPROACH; USEFUL SKEW TREE (UST);

TIMING CIRCUITS;

EID: 0031169289     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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