UST/DME: A clock tree router for general skew constraints

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 400-405

  Tsao, Chung Wen Albert ^a   Koh, Cheng Kok ^b  

^a Ultima Interconnect Technology   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; ALGORITHMS; CLOCK DISTRIBUTION NETWORKS; CLOCKS; FORESTRY; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; GRAPH THEORY; LOGIC DESIGN; SCHEDULING;

BOUNDED SKEW; CLOCK ROUTING; DEFERRED-MERGE EMBEDDING; LAYOUT SYNTHESIS; NEW APPROACHES; ROUTING PROBLEMS; SKEW SCHEDULING; USEFUL SKEW TREES;

COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT;

CLOCK LAYOUT SYNTHESIS; CLOCK TREE ROUTER; DEFERRED MERGE EMBEDDING; USEFUL SKEW TREE;

EID: 0034478055     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896505     Document Type: Conference Paper

References (17)

1. T.-H. Chao, Y.-C. Hsu Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wire- length. IEEE Trans, on Circuits and Systems, 39(11):799- 814, November 1992.
2. J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. A. Tsao. Bounded-skew clock and Steiner routing. ACM Trans, on Design Automation of Electronics Systems, 3(3):341-388, 1998.
3. T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms, chapter 25.5, pages 539-543. 1990.
4. R. B. Deokar and S. S. Sapatnekar. A graph-theoretic approach to clock skew optimization. In Proc. IEEE Int. Symp. on Circuits and Systems, pages 407-410, 1994.
5. M. Edahiro. Minimum path-length equi-distant routing. In Proc. IEEE Asia-Pacific Conf. on Circuits and Systems, pages 41-46, December 1992.
6. M. Edahiro. An efficient zero-skew routing algorithm. In Proc. Design Automation Conf, pages 375-380, June 1994.
7. J. R Fishburn. Clock skew optimization. IEEE Trans, on Computers, 39(7):945-951, July 1990.
8. A. B. Kahng and C.-W. A. Tsao. Practical bounded-skew clock routing. Journal of VLSI Signal Processing (Special issue on High Performance Clock Distribution Networks), 16(2-3): 199-215, June-July 1997.
9. J. L. Neves and E. G. Friedman. Optimal clock skew scheduling tolerant to process variations. In Proc. Design Automation Conf, pages 623-628, 1996.
10. K. A. Sakallah, T. N. Mudge, and O. A. Olukotun. checkTc and minTc: Timing verification and optimal clocking of synchronous digital circuits. In Proc. Int. Conf. on Computer Aided Design, pages 552-555, 1990.
11. N. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. Graph algorithms for clock schedule optimization. In Proc. Int. Conf. on Computer Aided Design, pages 132-136, 1992.
12. T.G. Szymanski. Computing optimal clock schedules. In Proc. Design Automation Conf, pages 399-404, 1992.
13. R.-S. Tsay. An exact zero-skew clock routing algorithm. IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, CAD-12(2):242-249, February 1993.
14. A. Vittal, H. Ha, F. Brewer, and M. Marek-Sadowska. Clock skew optimization for ground bounce control. In Proc. Int'l Conf. on Computer Aided Design, pages 395-399, Nov. 1996.
15. P. Vuillod, L. Benini, A. Bogliolo, and G. De Micheli. Clock- skew optimization for peak current reduction. In Proc. Int'l Symp. on Low Power Electronics and Design, pages 265-270, Aug. 1996.
16. J. G. Xi and W. W.-M. Dai. Jitter-tolerant clock routing in two-phase synchronous systems. In Proc. Int. Conf. on Computer Aided Design, pages 316-320, 1996.
17. J. G. Xi and W. W.-M. Dai. Useful-skew clock routing with gate sizing for low power design. Journal of VLSI Signal Processing Systems, 16(2/3): 163-170, 1996.